TC1303C-1A1EMF
| Model | TC1303C-1A1EMF |
| Description | 0.5 A SWITCHING REGULATOR, 2400 kHz SWITCHING FREQ-MAX, PDSO10, 3 X 3 MM, 0.9 MM HEIGHT, PLASTIC, DFN-10 |
| PDF file | Total 38 pages (File size: 756K) |
| Chip Manufacturer | MICROCHIP |
TC1303A/TC1303B/TC1303C/TC1304
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
TABLE 3-1:
PIN FUNCTION TABLE
Symbol
Pin No.
TC1303
TC1304
Description
MSOP, DFN MSOP, DFN
1
1
2
3
4
5
6
7
7
8
9
10
11
SHDN2
—
V
IN2
V
OUT2
PG
A
GND
V
FB
/V
OUT1
SHDN1
—
V
IN1
L
X
P
GND
EP
—
SHDN
V
IN2
V
OUT2
PG
A
GND
V
FB
/V
OUT1
—
A
GND
V
IN1
L
X
P
GND
EP
Active Low Shutdown Input for LDO Output Pin
Active Low Shutdown Input both Buck Regulator Output and LDO Output.
Initiates sequencing up and down
Analog Input Supply Voltage Pin
LDO Output Voltage Pin
Power-Good Output Pin
Analog Ground Pin
Buck Feedback Voltage (Adjustable Version) / Buck Output Voltage
(Fixed Version) Pin
Active Low Shutdown Input for Buck Regulator Output Pin
Analog Ground Pin
Buck Regulator Input Voltage Pin
Buck Inductor Output Pin
Power Ground Pin
Exposed Pad - For the DFN package, the center exposed pad is a thermal
path to remove heat from the device. Electrically this pad is at ground
potential and should be connected to A
GND
.
3.1
TC1303 LDO Shutdown Input Pin
(SHDN2)
3.4
LDO Output Voltage Pin (V
OUT2
)
SHDN2 is a logic-level input used to turn the LDO
Regulator on and off. A logic-high (> 45% of V
IN
), will
enable the regulator output. A logic-low (< 15% of V
IN
)
will ensure that the output is turned off.
V
OUT2
is a regulated LDO output voltage pin. Connect
a 1 µF or larger capacitor to V
OUT2
and A
GND
for proper
operation.
3.5
Power-Good Output Pin (PG)
3.2
TC1304 Shutdown Input Pin
(SHDN)
SHDN is a logic-level input used to initiate the
sequencing of the LDO output, then the buck regulator
output. A logic-high (> 45% of V
IN
), will enable the
regulator outputs. A logic-low (< 15% of V
IN
) will ensure
that the outputs are turned off.
PG is an output level indicating that V
OUT2
(LDO) is
within 94% of regulation. The PG output is configured
as a push-pull for the TC1303B and open-drain output
for the TC1303A, TC1303C and TC1304.
3.6
Analog Ground Pin (A
GND
)
3.3
LDO Input Voltage Pin (V
IN2
)
A
GND
is the analog ground connection. Tie A
GND
to the
analog portion of the ground plane (A
GND
). See the
physical layout information in
for grounding recommendations.
V
IN2
is a LDO power input supply pin. Connect variable
input voltage source to V
IN2
.
Connect V
IN1
and V
IN2
together with board traces as short as possible. V
IN2
provides the input voltage for the LDO. An additional
capacitor can be added to lower the LDO regulator
input ripple voltage.
3.7
Buck Regulator Output Sense Pin
(V
FB
/V
OUT1
)
For V
OUT1
adjustable-output voltage options, connect
the center of the output voltage divider to the V
FB
pin.
For fixed-output voltage options, connect the output of
the buck regulator to this pin (V
OUT1
).
©
2008 Microchip Technology Inc.
DS21949C-page 19
