TC1303C-1A1EMF
| Model | TC1303C-1A1EMF |
| Description | 0.5 A SWITCHING REGULATOR, 2400 kHz SWITCHING FREQ-MAX, PDSO10, 3 X 3 MM, 0.9 MM HEIGHT, PLASTIC, DFN-10 |
| PDF file | Total 38 pages (File size: 756K) |
| Chip Manufacturer | MICROCHIP |
TC1303A/TC1303B/TC1303C/TC1304
As an example, for a 3.6V input, 1.8V output with a load
of 400 mA, the efficiency taken from
is
approximately 84%. The internal power dissipation is
approximately 137 mW.
returns are connected closely together at the P
GND
plane. The LDO optional input capacitor (C
IN2
) and
LDO output capacitor C
OUT2
are returned to the A
GND
plane. The analog ground plane and power ground
plane are connected at one point (shown near L
1
). All
other signals (SHDN1, SHDN2, feedback in the
adjustable-output case) should be referenced to A
GND
and have the A
GND
plane underneath them.
-
Via
5.6.2
LDO OUTPUT (V
OUT2
)
The internal power dissipation within the TC1303/
TC1304 LDO is a function of input voltage, output
voltage and output current.
can be used
to calculate the internal power dissipation for the LDO.
A
GND
to P
GND
+V
OUT1
L
1
EQUATION 5-7:
P
LDO
=
(
V
IN
(
MAX
) )
–
V
OUT2
(
MIN
)
)
×
I
OUT2
(
MAX
) )
Where:
P
LDO
= LDO Pass device internal power
dissipation
V
IN(MAX)
= Maximum input voltage
V
OUT(MIN)
= LDO minimum output voltage
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package’s maximum
internal power dissipation.
+V
IN2
+V
OUT2
C
OUT2
* C
IN2
Optional
C
OUT1
A
GND
C
IN2
1
2
3
4
5
P
GND
10
9
8
7
TC1303B
6
A
GND
Plane
P
GND
Plane
C
IN1
+V
IN1
A
GND
FIGURE 5-1:
Component Placement,
Fixed 10-Pin MSOP.
There will be some difference in layout for the 10-pin
DFN package due to the thermal pad. A typical fixed-
output DFN layout is shown below. For the DFN layout,
the V
IN1
to V
IN2
connection is routed on the bottom of
the board around the TC1303/TC1304 thermal pad.
- Via
5.6.3
LDO POWER DISSIPATION
EXAMPLE
Input Voltage
V
IN
= 5V±10%
LDO Output Voltage and Current
V
OUT
= 3.3V
I
OUT
= 300 mA
Internal Power Dissipation
P
LDO(MAX)
= (V
IN(MAX)
– V
OUT2(MIN)
) x I
OUT2(MAX)
P
LDO
= (5.5V – 0.975 x 3.3V) x 300 mA
P
LDO
= 684.8 mW
A
GND
to P
GND
+V
OUT1
*
C
IN2
Optional
A
GND
C
OUT1
PGND
C
IN2
+V
IN2
+V
OUT2
C
OUT2
L
1
1
2
3
4
5
5.7
PCB Layout Information
Some basic design guidelines should be used when
physically placing the TC1303/TC1304 on a Printed
Circuit Board (PCB). The TC1303/TC1304 has two
ground pins, identified as A
GND
(analog ground) and
P
GND
(power ground). By separating grounds, it is
possible to minimize the switching frequency noise on
the LDO output. The first priority, while placing external
components on the board, is the input capacitor (C
IN1
).
Wiring should be short and wide; the input current for
the TC1303/TC1304 can be as high as 800 mA. The
next priority would be the buck regulator output
capacitor (C
OUT1
) and inductor (L
1
). All three of these
components are placed near their respective pins to
minimize trace length. The C
IN1
and C
OUT1
capacitor
10
9
8
7
6
P
GND
C
IN1
+V
IN1
A
GND
TC1303B
P
GND
Plane
A
GND
Plane
FIGURE 5-2:
Component Placement,
Fixed 10-Pin DFN.
©
2008 Microchip Technology Inc.
DS21949C-page 27
