K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.21 TIMING WAVEFORM OF MULTIPLE WRITE CYCLE(Low ADV Type)
( OE=V
IH
, WAIT=High-Z, WE Controlled)
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADV
t
WC
Address
t
AW
t
CW
CS
t
BW
UB, LB
t
WP
WE
t
AS
t
DH
t
DW
Data Valid
t
WHP
t
AS
t
DH
t
DW
Data Valid
t
WP
t
BW
t
WR
t
AW
t
CW
t
WR
t
WC
Data in
Data out
High-Z
High-Z
(LOW ADV TYPE MULTIPLE WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high or WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS or WE going high.
5. Clock input does not have any affect to the asynchronous multiple write operation if t
WHP
is shorter than (Read Latency - 1) clock
duration.
6. t
WP
(min)=70ns for continuous write operation over 50 times.
Table 25. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS
(Low ADV Type Multiple Write, WE Controlled)
Symbol
Min
t
WC
t
CW
t
AW
t
BW
t
WP
70
60
60
60
55
1)
Speed
Max
-
-
-
-
-
ns
ns
ns
ns
ns
t
WHP
t
AS
t
WR
t
DW
t
DH
Units
Symbol
Min
5ns
0
0
30
0
Speed
Max
Latency-1 clock
-
-
-
-
-
ns
ns
ns
ns
Units
1. tWC(min)=90ns or t
WP
(min)=70ns for continuous write operation over 50 times.
- 25 -
Revision 1.0
April 2005
