K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.36 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM
[Latency=5, Burst Length=4]
0
T
CLK
t
ADVS
ADV
t
AS(B)
Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
t
ADVH
t
BEADV
t
AH(B)
Don’t Care
t
AS(B)
Valid
t
AH(B)
t
CSS(B)
CS
t
BC
t
WES
t
CSS(B)
t
BC
t
WEH
WE
t
OEL
OE
t
BEL
LB, UB
Latency 5
Data in
Latency 5
Data out
t
WL
WAIT
High-Z
High-Z
t
WH
t
CD
High-Z
t
OH
DQ0 DQ1 DQ2 DQ3
D0
D1
D2
t
BS
t
BH
t
DS
t
DHC
D3
t
HZ
High-Z
t
WL
t
WH
t
WZ
t
WZ
(SYNCHRONOUS BURST READ & WRITE CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 40. BURST READ to BURST WRITE AC CHARACTERISTICS
Symbol
Min
t
BEADV
7
Speed
Max
-
ns
Units
Symbol
Min
Speed
Max
Units
- 40 -
Revision 1.0
April 2005
