K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
UtRAM
Fig.34 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4]
0
CLK
t
ADVS
ADV
t
AS(A)
Address
Valid
1
2
3
4
5
6
7
8
9
10
11
T
12
13
14
15
16
17
18
19
20
t
ADVH
t
ADV
t
AH(A)
Don’t Care
t
AH(B)
t
AS(B)
Valid
Don’t Care
t
AW
t
CSS(A)
CS
t
CW
t
WLRL
WE
t
AS
t
WP
t
CSS(B)
t
BC
t
OEL
OE
t
BW
LB, UB
t
DW
Data in
t
DH
t
BEL
Data Valid
Latency 5
t
CD
t
OH
DQ0 DQ1 DQ2 DQ3
t
HZ
Data out
High-Z
Read Latency 5
High-Z
t
WL
t
WH
t
WZ
WAIT
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
Table 38. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS
Symbol
Min
t
WLRL
1
Speed
Max
-
clock
Units
Symbol
Min
Speed
Max
Units
- 38 -
Revision 1.0
April 2005
