K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
Fig.27 TIMING WAVEFORM OF BURST WRITE CYCLE(1)
[Latency=5,Burst Length=4,WP=Low enable](OE=V
IH
)
- CS Toggling Consecutive Burst Write
0
T
CLK
t
ADVH
t
ADVS
ADV
t
BEADV
t
AS(B)
Address
t
CSS(B)
CS
t
BS
t
BH
LB, UB
t
WEH
WE
t
WES
t
DS
Latency 5
Data in
t
WL
WAIT
High-Z
t
WH
t
DHC
D0
D1
D2
t
DHC
D3
t
WZ
t
WL
t
WH
Latency 5
t
WHP
t
BMS
t
BMH
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
t
AH(B)
Don’t Care
Valid
t
BC
t
CSHP
(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
4. D2 is masked by UB and LB.
5. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 31. BURST WRITE AC CHARACTERISTICS
(CS Toggling Consecutive Burst)
Symbol
Min
t
CSHP
t
BS
t
BH
t
BMS
t
BMH
t
WES
t
WEH
5
5
5
7
7
5
5
Speed
Max
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WHP
t
DS
t
DHC
t
WL
t
WH
t
WZ
Units
Symbol
Min
5
5
3
-
-
-
Speed
Max
-
-
-
10
12
12
ns
ns
ns
ns
ns
ns
Units
- 31 -
∼
∼
D0
Revision 1.0
April 2005
