K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM
UtRAM
Fig.30 TIMING WAVEFORM OF BURST WRITE STOP by CS
[Latency=5,Burst Length=4,WP=Low enable](OE=V
IH
)
0
T
CLK
t
ADVH
t
ADVS
ADV
t
AS(B)
Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
t
AH(B)
Don’t Care
t
BSADV
Valid
t
CSS(B)
CS
t
BS
t
BH
LB, UB
t
WEH
WE
t
WES
t
DS
Latency 5
Data in
t
WL
t
WH
WAIT
High-Z
D0
t
CSLH
t
CSHP
t
WHP
t
DHC
D1
t
WZ
t
WL
High-Z
(SYNCHRONOUS BURST WRITE STOP TIMING)
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 34. BURST WRITE STOP AC CHARACTERISTICS
Symbol
Min
t
BSADV
t
CSLH
t
CSHP
t
BS
t
BH
t
WES
t
WEH
12
7
5
5
5
5
5
Speed
Max
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WHP
t
DS
t
DHC
t
WL
t
WH
t
WZ
Units
Symbol
Min
5
5
3
-
-
-
Speed
Max
-
-
-
10
12
12
ns
ns
ns
ns
ns
ns
Units
- 34 -
∼
∼
Latency 5
D0
t
WH
D1
D2
Revision 1.0
April 2005
