K1B3216BDD-FI700
| Model | K1B3216BDD-FI700 |
| Description | Memory IC, 2MX16, CMOS, PBGA54 |
| PDF file | Total 42 pages (File size: 735K) |
| Chip Manufacturer | SAMSUNG |
K1B3216BDD
SYNCHRONOUS BURST READ TIMING WAVEFORM
Fig.25 TIMING WAVEFORM OF BURST READ CYCLE(2)
[Latency=5,Burst Length=4,WP=Low enable](WE=V
IH
)
- CS Low Holding Consecutive Burst Read
0
T
CLK
t
ADVH
t
ADVS
ADV
t
BEADV
t
AS(B)
Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
AH(B)
Don’t Care
Valid
t
CSS(B)
CS
t
BEL
LB, UB
t
BLZ
t
OEL
OE
t
OLZ
Latency 5
Data out
t
WL
WAIT
High-Z
t
BC
t
CD
Undefined
t
OH
DQ0
DQ1
DQ2
DQ3
t
WH
(SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
5. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 29. BURST READ AC CHARACTERISTICS
(CS Low Holding Consecutive Burst)
Symbol
Min
t
BEL
t
OEL
t
BLZ
t
OLZ
t
HZ
1
1
5
5
-
Speed
Max
-
-
-
-
12
clock
clock
ns
ns
ns
t
CD
t
OH
t
WL
t
AWL
t
WH
Units
Symbol
Min
-
3
-
-
-
Speed
Max
10
-
10
10
12
ns
ns
ns
ns
ns
Units
- 29 -
∼
∼
t
HZ
t
AWL
t
WH
Revision 1.0
April 2005
