G1-266P-85-1.8
| Model | G1-266P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
4.3
MEMORY CONTROLLER
MHz and 100 MHz. The core clock can be divided down
from 2 to 5 in half clock increments to generate the SDRAM
clock. SDRAM frequencies between 79 MHz and 100 MHz
are only supported for certain types of closed systems and
strict design rules must be adhered to. For further details,
contact your local National Semiconductor technical sup-
port representative.
A basic block diagram of the memory controller is shown in
The memory controller arbitrates requests from the X-Bus
(processor and PCI), display controller, and graphics pipe-
line. A total of 512 MB of SDRAM memory is supported.
The GX1 processor supports LVTTL (low voltage TTL)
technology. LVTTL technology allows the SDRAM interface
of the memory controller to run at frequencies up to 100
MHz.
The SDRAM clock is a function of the core clock. The
SDRAM bus can be run at speeds that range between 66
RFSH
Processor/PCI
Control
Display Controller
Control
Graphics Pipeline
Control
Processor/PCI I/F
SDRAM
Sequence
Controller
DQM[7:0]
RASA#,RASB#
Display Controller I/F
Arbiter
Timing
Controller
CASA#,CASB#
CS[3:0]#
WEA#/WEB#
Graphics Pipeline I/F
CKEA, CKEB
Configuration
Registers
Processor/PCI Address
Display Controller Address
Graphics Pipeline Address
Processor/PCI
Write Buffer (16 Bytes)
Address
Control/MUX
MA[12:0]
BA[1:0]
Processor/PCI Data
Display Controller Data
Display Controller
Write Buffer (16 Bytes)
MD[63:0]
Graphics Pipeline Data
Graphics Controller
Write Buffer (16 Bytes)
Read Buffer
(16 Bytes)
Clock Divider
2, 2.5, 3, 3.5, 4, 4.5, 5
Core Clock (ph2)
SDCLK[3:0]
Figure 4-3. Memory Controller Block Diagram
Revision 1.0
107
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