G1-266P-85-1.8
| Model | G1-266P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
Table 8-29. FPU Instruction Set Summary (Continued)
FPU Instruction
FDIV
Floating Point Divide
Top of Stack
80-bit Register
64-bit Real
32-bit Real
FDIVP
Floating Point Divide, Pop
FDIVR
Floating Point Divide Reversed
Top of Stack
80-bit Register
64-bit Real
32-bit Real
FDIVRP
Floating Point Divide Reversed, Pop
FIDIV
Floating Point Integer Divide
32-bit Integer
16-bit Integer
FIDIVR
Floating Point Integer Divide Reversed
32-bit Integer
16-bit Integer
FFREE
Free Floating Point Register
FINCSTP
Increment Stack Pointer
FINIT
Initialize FPU
FNINIT
Initialize FPU
FLD
Load Data to FPU Register
Top of Stack
80-bit Real
64-bit Real
32-bit Real
FBLD
Load Packed BCD Data to FPU Register
FILD
Load Integer Data to FPU Register
64-bit Integer
32-bit Integer
16-bit Integer
FLD1
Load Floating Const.= 1.0
FLDCW
Load FPU Mode Control Register
FLDENV
Load FPU Environment
FLDL2E
Load Floating Const.= Log2(e)
FLDL2T
Load Floating Const.= Log2(10)
FLDLG2
Load Floating Const.= Log10(2)
FLDLN2
Load Floating Const.= Ln(2)
FLDPI
Load Floating Const.=
π
FLDZ
Load Floating Const.= 0.0
FMUL
Floating Point Multiply
Top of Stack
80-bit Register
64-bit Real
32-bit Real
FMULP
Floating Point Multiply & Pop
FIMUL
Floating Point Integer Multiply
32-bit Integer
16-bit Integer
DA [mod 001 r/m]
DE [mod 001 r/m]
TOS <--- TOS
×
M.SI
TOS <--- TOS
×
M.WI
9 - 11
8 - 10
DC [1100 1 n]
D8 [1100 1 n]
DC [mod 001 r/m]
D8 [mod 001 r/m]
DE [1100 1 n]
ST(n) <--- ST(n)
×
TOS
TOS <--- TOS
×
ST(n)
TOS <--- TOS
×
M.DR
TOS <--- TOS
×
M.SR
ST(n) <--- ST(n)
×
TOS; then pop TOS
4-9
4-9
4-8
4-6
4-9
DF [mod 101 r/m]
DB [mod 000 r/m]
DF [mod 000 r/m]
D9 E8
D9 [mod 101 r/m]
D9 [mod 100 r/m]
D9 EA
D9 E9
D9 EC
D9 ED
D9 EB
D9 EE
Push M.LI onto stack
Push M.SI onto stack
Push M.WI onto stack
Push 1.0 onto stack
Ctl Word <--- Memory
Env Regs <--- Memory
Push Log
2
(e) onto stack
Push Log
2
(10) onto stack
Push Log
10
(2) onto stack
Push Log
e
(2) onto stack
Push
π
onto stack
Push 0.0 onto stack
4-8
4-6
3-6
4
4
30
4
4
4
4
4
4
D9 [1100 0 n]
DB [mod 101 /m]
DD [mod 000 r/m]
D9 [mod 000 r/m]
DF [mod 100 r/m]
Push ST(n) onto stack
Push M.XR onto stack
Push M.DR onto stack
Push M.SR onto stack
Push M.BCD onto stack
2
2
2
2
41 - 45
DA [mod 111 r/m]
DE [mod 111 r/m]
DD [1100 0 n]
D9 F7
(9B)DB E3
DB E3
TOS <--- M.SI / TOS
TOS <--- M.WI / TOS
TAG(n) <--- Empty
Increment top-of-stack pointer
Wait, then initialize
Initialize
34 - 38
34 - 38
4
2
8
6
DA [mod 110 r/m]
DE [mod 110 r/m]
TOS <--- TOS / M.SI
TOS <--- TOS / M.WI
34 - 38
34 - 38
DC [1111 0 n]
D8 [1111 1 n]
DC [mod 111 r/m]
D8 [mod 111 r/m]
DE [1111 0 n]
TOS <--- ST(n) / TOS
ST(n) <--- TOS / ST(n)
TOS <--- M.DR / TOS
TOS <--- M.SR / TOS
ST(n) <--- TOS / ST(n); then pop TOS
24 - 34
24 - 34
24 - 34
24 - 34
24 - 34
DC [1111 1 n]
D8 [1111 0 n]
DC [mod 110 r/m]
D8 [mod 110 r/m]
DE [1111 1 n]
ST(n) <--- ST(n) / TOS
TOS <--- TOS / ST(n)
TOS <--- TOS / M.DR
TOS <--- TOS / M.SR
ST(n) <--- ST(n) / TOS; then pop TOS
24 - 34
24 - 34
24 - 34
24 - 34
24 - 34
Opcode
Operation
Clock
Count
Issue
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