G1-266P-85-1.8
| Model | G1-266P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-35. Standard VGA Modes
Category
Software
Mode
0,1
2,3
4,5
6
7
Hardware
0Dh
0Eh
0Fh
10h
11h
12h
13h
Text or Graphics
Text
Text
Graphics
Graphics
Text
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Resolution
40x25
80x25
320x200
640x200
80x25
320x200
640x200
640x350
640x350
640x480
640x480
320x200
Format
Characters
Characters
2-bpp
1-bpp
Characters
4-bpp
4-bpp
1-bpp
4-bpp
1-bpp
4-bpp
8-bpp
Type
CGA
CGA
CGA
CGA
MDA
EGA
EGA
EGA
EGA
VGA
VGA
VGA
A VGA is made up of several functional units.
•
The
frame buffer
is 256 KB of memory that provides
data for the video display. It is organized as 64 K 32-bit
DWORDs.
•
The
sequencer
decomposes word and DWORD CPU
accesses into byte operations for the graphics
controller. It also controls a number of miscellaneous
functions, including reset and some clocking controls.
•
The
graphics controller
provides most of the interface
between CPU data and the frame buffer. It allows the
programmer to read and write frame buffer data in
different formats. Plus provides ROP (raster operation)
and masking functions.
•
The
CRT controller
provides video timing signals and
address generation for video refresh. It also provides a
text cursor.
•
The
attribute controller
contains the video refresh
datapath, including text rasterization and palette
lookup.
•
The
general registers
provide status information for
the programmer as well as control over VGA-host
address mapping and clock selection. This is all
handled in hardware by the graphics pipeline.
It is important to understand that a VGA is constructed of
numerous independent functions. Most of the register
fields correspond to controls that were originally built out
of discrete logic or were part of a dedicated controller
such as the 6845. The notion of a VGA “mode” is a higher-
level convention to denote a particular set of values for the
registers. Many popular programs do not use standard
modes, preferring instead to produce their own VGA set-
ups that are optimal for their purposes.
4.6.1.1 VGA Memory Organization
The VGA memory is organized as 64K 32-bit DWORDs.
This organization is usually presented as four 64 KB
“planes”. A plane consists of one byte out of every
DWORD. Thus, plane 0 refers to the least significant byte
from every one of the 64K DWORDs. The addressing
granularity of this memory is a DWORD, not a byte; that is,
consecutive addresses refer to consecutive DWORDs.
The only provision for byte-granularity addressing is the
four-byte enable signals used for writes. In C parlance,
single_plane_byte = (dword_fb[address] >>
(plane * 8)) & 0xFF;
When dealing with VGA, it is important to recognize the
distinction between host addresses, frame buffer
addresses, and the refresh address pipe. A VGA control-
ler contains a lot of hardware to translate between these
address spaces in different ways, and understanding
these translations is critical to understanding the entire
device. In standard four-plane graphics modes, a frame-
buffer DWORD provides eight 4-bit pixels. The left-most
pixel comes from bit 7 of each plane, with plane 3 provid-
ing the most significant bit.
pixel[i].bit[j] = dword_fb[address].bit[i*8 + (7-j)]
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