I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM8.
Problem:
FREEZE_WHILE_SMM Does Not Prevent Event From Pending
PEBS During SMM
In general, a PEBS record should be generated on the first count of the event after the
counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM
(MSR 1D9H, bit [14]) prevents performance counters from counting during SMM
(System Management Mode). Due to this erratum, if
1. A performance counter overflowed before an SMI
2. A PEBS record has not yet been generated because another count of the event has
not occurred
3. The monitored event occurs during SMM
then a PEBS record will be saved after the next RSM instruction.
When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event
occurs outside of SMM.
Implication:
A PEBS record may be saved after an RSM instruction due to the associated
performance counter detecting the monitored event during SMM; even when
FREEZE_WHILE_SMM is set.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
None identified.
Status:
HSM9.
Problem:
APIC Error “Received Illegal Vector” May be Lost
APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error
Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector
error is received on the same internal clock that the ESR is being written (as part of the
write-read ESR access flow). The corresponding error interrupt will also not be
generated for this case.
Due to this erratum, an incoming illegal vector error may not be logged into ESR
properly and may not generate an error interrupt.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
None identified.
Status:
HSM10.
Problem:
Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Under complex microarchitectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Memory ordering may be violated. Intel has not observed this erratum with any
commercially available software.
Implication:
Workaround:
Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status:
For the steppings affected, see the
Summary Table of Changes.
22
Specification Update
