I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM93.
Problem:
Implication:
Event Injection by VM Entry May Use an Incorrect B Flag for SS
The stack accesses made by VM-entry event injection may use an incorrect value for
the B flag (default stack-pointer size and upper bound) for the stack segment (SS).
An affected stack access may use an incorrect address or an incorrect segment upper
bound. This may result in unpredictable system behavior.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM94.
Problem:
LPDDR3 ZQ Calibration Following Deep Package C-state Exit May Lead
to Unpredictable System Behavior
Due to this erratum, upon exit from Package C7 or deeper, the processor issues
LPDDR3 ZQ calibration for dual die package or quad die package DRAMs in parallel
instead of serially as required by the LPDDR3 spec for those devices.
A deep Package C-state exit on systems using LPDDR3 dual die package or quad die
package DRAM may lead to unpredictable system behavior. Systems using LPDDR3
single die package DRAM or DDR3L memory are not affected.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM95.
Problem:
A Fault in SMM May Result in Unpredictable System Behavior
The value of the SS register as well as the current privilege level (CPL) may be
incorrect following a fault in SMM (system-management mode). The erratum can occur
only if a fault occurs following an SMI (system-management interrupt) and before
software has loaded the SS register (e.g., with the MOV SS instruction).
This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
None identified.
Status:
HSM96.
Problem:
Processor Frequency is Unexpectedly Limited Below Nominal P1 When
cTDP Down is Enabled
When cTDP (Configurable Thermal Design Power) Down is enabled on a processor
branded as Core
®
i3 or Pentium
®
, the processor frequency will be limited to cTDP
Down P1 frequency (Max Non-Turbo Frequency) when it should be able to operate
between the cTDP Down frequency P1 and the nominal P1 frequency.
When cTDP is enabled, the processor cannot achieve expected frequencies.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
HSM97.
Problem:
Implication:
PMI May be Signaled More Than Once For Performance Monitor
Counter Overflow
Due to this erratum, PMI (Performance Monitoring Interrupt) may be repeatedly issued
until the counter overflow bit is cleared in the overflowing counter.
Multiple PMIs may be received when a performance monitor counter overflows.
Workaround:
None identified. If the PMI is programmed to generate an NMI, software may delay the
EOI (end-of- Interrupt) register write for the interrupt until after the overflow
indications have been cleared.
Specification Update
43
