I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM45.
Problem:
Implication:
Status:
Display May Flicker When Package C-States Are Enabled
When package C-States are enabled, the display may not be refreshed at the correct
rate.
When this erratum occurs, the user may observe flickering on the display.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
HSM46.
Problem:
Implication:
Certain Combinations of AVX Instructions May Cause Unpredictable
System Behavior
Execution of certain combinations of AVX instructions may lead to unpredictable system
behavior.
When this erratum occurs, unpredictable system behaviors, including system hang or
incorrect results can occur.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM47.
Problem:
Processor May Incorrectly Estimate Peak Power Delivery
Requirements
Under certain conditions, the processor may incorrectly calculate the frequency at
which the cores and graphics engine can operate while still meeting voltage regulator
and power supply peak power delivery capabilities. When this occurs, combined with
high power workloads, system shutdown may be observed.
When this erratum occurs, system shutdown may be observed under high power
workloads.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM48.
Problem:
Implication:
IA32_PERF_CTL MSR is Incorrectly Reset
The IA32_PERF_CTL MSR (199H) is not initialized correctly after a processor reset.
If software reads the IA32_PERF_CTL MSR before writing it, software can observe an
incorrect reset value. Although incorrect values are reported to software, the correct
default values for this register are still used by the processor. No performance or power
impact occurs due to this erratum.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM49.
Problem:
Processor May Hang During a Function Level Reset of the Display
When package C-States are enabled, it is possible that the processor may hang when
software performs a Function Level Reset of the display via bit 1 of the Advanced
Features Control Register (Bus 0; Device 2; Function 0;
Offset
0A8H).
When this erratum occurs, the processor may hang.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
32
Specification Update
