I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM11.
Problem:
Performance Monitor Precise Instruction Retired Event May Present
Wrong Indications
When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated
(INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS
mode), the processor may return wrong PEBS/PMI interrupts and/or incorrect counter
values if the counter is reset with a SAV below 100 (Sample-After-Value is the
counter
reset value software programs
in
MSR IA32_PMC1[47:0] in order to control interrupt
frequency).
Due to this erratum, when using low SAV values, the program may get incorrect PEBS
or PMI interrupts and/or an invalid counter state.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
The sampling driver should avoid using SAV<100.
Status:
HSM12.
Problem:
CR0.CD Is
Ignored in VMX
Operation
If CR0.CD=1, the MTRRs and PAT should be ignored and the UC memory type should
be used for all memory accesses. Due to this erratum, a logical processor in VMX
operation will operate as if CR0.CD=0 even if that bit is set to 1.
Algorithms that rely on cache disabling may not function properly in VMX operation.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
Algorithms that rely on cache disabling should not be executed in VMX root operation.
HSM13.
Problem:
Instruction Fetch May Cause Machine Check if Page Size and Memory
Type Was Changed Without Invalidation
This erratum may cause a machine-check error (IA32_MCi_STATUS.MCACOD=0150H)
on the fetch of an instruction that crosses a 4-KByte address boundary. It applies only
if (1) the 4-KByte linear region on which the instruction begins is originally translated
using a 4-KByte page with the WB memory type; (2) the paging structures are later
modified so that linear region is translated using a large page (2-MByte, 4-MByte, or 1-
GByte) with the UC memory type; and (3) the instruction fetch occurs after the paging-
structure modification but before software invalidates any TLB entries for the linear
region.
Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Implication:
Workaround:
Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses; and then
modify the relevant paging-structure entry to set the P flag and establish the new page
size and memory type.
Status:
For the steppings affected, see the
Summary Table of Changes.
Specification Update
23
