I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
Errata (Sheet 1 of 5)
Steppings
Number
C-0
HSM1
HSM2
HSM3
HSM4
HSM5
HSM6
HSM7
HSM8
HSM9
HSM10
HSM11
HSM12
HSM13
HSM14
HSM15
HSM16
HSM17
HSM18
HSM19
HSM20
HSM21
HSM22
HSM23
HSM24
HSM25
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HSM26
HSM27
HSM28
HSM29
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LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
LER MSRs May Be Unreliable
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also
Result in a System Hang
#GP on Segment Selector Descriptor that Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
FREEZE_WHILE_SMM Does Not Prevent Event From Pending
PEBS During SMM
APIC Error “Received Illegal Vector” May be Lost
Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Performance Monitor Precise Instruction Retired Event May Present
Wrong Indications
CR0.CD Is Ignored in VMX Operation
LER MSRs May Be Unreliable
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
Processor May Fail to Acknowledge a TLP Request
Interrupt From Local APIC Timer May Not Be Detectable While Being
Delivered
PCIe* Root-port Initiated Compliance State Transmitter Equalization
Settings May be Incorrect
PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s
Unused PCIe* Lanes May Report Correctable Errors
Accessing Physical Memory Space 0-640K through the Graphics
Aperture May Cause Unpredictable System Behavior
PCIe Root Port May Not Initiate Link Speed Change
Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/
POP SS is Followed by a Store or an MMX Instruction
VEX.L is Not Ignored with VCVT*2SI Instructions
Processor May Shut Down During Boundary Scan Testing
Certain Local Memory Read / Load Retired PerfMon Events May
Undercount
Specific Graphics Blitter Instructions May Result in Unpredictable
Graphics Controller Behavior
Processor May Enter Shutdown Unexpectedly on a Second
Uncorrectable Error
Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates
Do Not Follow PCIe* Specification
Status
ERRATA
Specification Update
9
