I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM28.
Problem:
Processor May Enter Shutdown Unexpectedly on a Second
Uncorrectable Error
If an IA32_MCi_STATUS MSR contains an uncorrectable error with MCACOD=0x406 and
a second uncorrectable error occurs after warm reset but before the first error is
cleared by zeroing the IA32_MCi_STATUS MSR, a shutdown will occur.
When this erratum occurs, the processor will unexpectedly shut down instead of
executing the machine check handler.
Implication:
Workaround:
None identified. Software should clear IA32_MCi_STATUS MSRs as early as possible to
minimize the possibility of this erratum occurring.
Status:
For the steppings affected, see the
Summary Table of Changes.
HSM29.
Problem:
Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates
Do Not Follow PCIe* Specification
The PCIe controller does not produce the PCIe specification defined sequence for the
Modified Compliance Pattern at 2.5 GT/s and 5 GT/s transfer rates. This erratum is not
seen at 8 GT/s transfer rates.
Normal PCIe operation is unaffected by this erratum.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
None identified.
HSM30.
Problem:
Performance Monitor Counters May Produce Incorrect Results
When operating with SMT enabled, a memory at-retirement performance monitoring
event (from the list below) may be dropped or may increment an enabled event on the
corresponding counter with the same number on the physical core’s other thread rather
than the thread experiencing the event. Processors with SMT disabled in BIOS are not
affected by this erratum.
The list of affected memory at-retirement events is as follows:
MEM_UOP_RETIRED.LOADS
MEM_UOP_RETIRED.STORES
MEM_UOP_RETIRED.LOCK
MEM_UOP_RETIRED.SPLIT
MEM_UOP_RETIRED.STLB_MISS
MEM_LOAD_UOPS_RETIRED.HIT_LFB
MEM_LOAD_UOPS_RETIRED.L1_HIT
MEM_LOAD_UOPS_RETIRED.L2_HIT
MEM_LOAD_UOPS_RETIRED.L3_HIT
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE
MEM_LOAD_UOPS_RETIRED.L3_MISS
MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM
MEM_LOAD_UOPS_RETIRED.L2_MISS
Implication:
Due to this erratum, certain performance monitoring event will produce unreliable
results during hyper-threaded operation.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
None identified.
Status:
28
Specification Update
