I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM24.
Problem:
VEX.L is Not Ignored with VCVT*2SI Instructions
The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and
VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and
will cause a #UD.
Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI,
VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.
Status:
HSM25.
Problem:
Processor May Shut Down During Boundary Scan Testing
If the HIGHZ TAP command is run before initializing the Boundary Scan chain, the
VR_EN pin may be tristated. The VR_EN pin may also be tristated by the EXTEST TAP
command. The VR_EN signal controls the external voltage regulator; tristating VR_EN
may disable the voltage regulator.
Due to this erratum, the processor may shut down.
Implication:
Workaround:
Initialize the Boundary Scan chain by running the PRELOAD TAP command before
running HIGHZ TAP command or EXTEST TAP command.
Status:
For the steppings affected, see the
Summary Table of Changes.
HSM26.
Problem:
Certain Local Memory Read / Load Retired PerfMon Events May
Undercount
Due to this erratum, the Local Memory Read / Load Retired PerfMon events listed below
may undercount.
MEM_LOAD_RETIRED.L3_HIT
MEM_LOAD_RETIRED.L3_MISS
MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT
MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM
MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM
MEM_LOAD_L4_RETIRED.LOCAL_HIT
MEM_TRANS_RETIRED.LOAD_LATENCY
Implication:
The affected events may undercount, resulting in inaccurate memory profiles. Intel has
observed undercounts as much as 40%.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
None identified.
Status:
HSM27.
Problem:
Implication:
Specific Graphics Blitter Instructions May Result in Unpredictable
Graphics Controller Behavior
Specific source-copy blitter instructions in Intel
®
HD Graphics 4600 Processor may
result in unpredictable behavior when a blit source and destination overlap.
Due to this erratum, the processor may exhibit unpredictable graphics controller
behavior. Intel has not observed this erratum with any commercially available software.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
None identified.
Status:
Specification Update
27
