I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
Status:
For the steppings affected, see the
Summary Table of Changes.
HSM75.
Problem:
Performance Monitoring Events May Report Incorrect Number of Load
Hits or Misses to LLC
The following performance monitor events should count the numbers of loads hitting or
missing LLC. However due to this erratum, The L3_hit related events may over count
and the L3_miss related events may undercount.
MEM_LOAD_RETIRED.L3_HIT (Event D1H, Umask 40H)
MEM_LOAD_RETIRED.L3_MISS (Event D1H, Umask 20H)
MEM_LOAD_L3_HIT_RETIRED. XSNP_NONE (Event D2H, Umask 08H)
MEM_LOAD_LLC_MISS_RETIRED. LOCAL_DRAM (Event D3H, Umask 01H)
Implication:
Status:
The listed performance monitoring events may be inaccurate.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
None identified.
HSM76.
Problem:
Performance Monitoring Event INSTR_RETIRED.ALL May Generate
Redundant PEBS Records For an Overflow
Due to this erratum, the performance monitoring feature PDIR (Precise Distribution of
Instructions Retired) for INSTR_RETIRED.ALL (Event C0H; Umask 01H) will generate
redundant PEBS (Precise Event Based Sample) records for a counter overflow. This can
occur if the lower 6 bits of the performance monitoring counter are not initialized or
reset to 0, in the PEBS counter reset field of the DS Buffer Management Area.
The above event count will under count on locked loads hitting the L2 cache.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
None identified.
HSM77.
Problem:
Locked Load Performance Monitoring Events May Under Count
The performance monitoring events MEM_TRANS_RETIRED.LOAD_LATENCY (Event
CDH; Umask 01H), MEM_LOAD_RETIRED.L2_HIT (Event D1H; Umask 02H), and
MEM_UOPS_RETIRED.LOCKED (Event DOH; Umask 20H) should count the number of
locked loads. Due to this erratum, these events may under count for locked
transactions that hit the L2 cache.
The above event count will under count on locked loads hitting the L2 cache.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
None identified.
HSM78.
Problem:
Implication:
Processor May Hang Upon Entrance to Package C6 or C7
If the processor exits a Package C8 or deeper state without waking either the IA Cores
or integrated graphics, a subsequent Package C6 or Package C7 entrance may hang.
Due to this erratum, when the processor attempts to enter Package C6 or Package C7
after exiting Package C8 or deeper states, it may hang.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
Specification Update
39
