I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
HSM119.
Problem:
A PEBS Record May Contain Processor State for an Unexpected
Instruction
If a performance counter has overflowed and is configured for PEBS (precise event-
based sampling), the processor will arm the PEBS hardware within a bounded number
of cycles called the skid (see the discussion of skid and related topics in the Precise
Distribution of Instructions Retired section of the Intel
®
64 and IA-32 Architectures
Software Developer Manual). Once the PEBS hardware is armed, the processor should
capture processor state in a PEBS record following the execution of the next instruction
that causes the counter to increment (a “triggering” instruction). Due to this erratum,
the capture of processor state may occur at an instruction after the first triggering
instruction following the skid but not beyond the second triggering instruction after the
skid.
A PEBS record may contain processor state (including instruction pointer) not
associated with the triggering instruction.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
None identified.
Status:
HSM120.
Problem:
Implication:
MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data
The MSR_PP1_ENERGY_STATUS MSR (641H) bits [31:0] reports incorrect energy data.
Due to this erratum, reported Intel Integrated Graphics domain energy consumption
may not be accurate.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM121.
Problem:
x87 FPU DP May be Incorrect After Instructions That Save FP State to
Memory
Under certain conditions, the value of the x87 FPU DP (Floating Point Unit Data Pointer)
saved by the FSAVE/FNSAVE, FSTENV/FNSTENV, FXSAVE, XSAVE, or XSAVEOPT
instructions may be incorrect.
Due to this erratum, the x87 FPU DP may be incorrect.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
HSM122.
Problem:
Implication:
Processor May Hang During Package C7 Exit
Under certain internal timing conditions, the processor might not properly exit package
C7 leading to a hang.
Due to this erratum, the package C7 state may not be reliable. Intel has not observed
this erratum with any commercially available system.
For the steppings affected, see the
Summary Table of Changes.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
Specification Update
49
