I3-4030Y
| Model | I3-4030Y |
| Description | Microprocessor, CMOS |
| PDF file | Total 58 pages (File size: 572K) |
| Chip Manufacturer | INTEL |
Status:
For the steppings affected, see the
Summary Table of Changes.
HSM40.
Problem:
PCIe* Controller May Initiate Speed Change While in DL_Init State
Causing Certain PCIe Devices to Fail to Train
The PCIe controller supports hardware autonomous speed change capabilities. Due to
this erratum, the PCIe controller may initiate speed change while in the DL_Init state
which may prevent link training for certain PCIe devices.
Certain PCIe devices may fail to complete DL_Init causing the PCIe link to fail to train.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
HSM41.
Problem:
Spurious VT-d Interrupts May Occur When the PFO Bit is Set
When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status]
register) is set to 1, further faults should not generate an interrupt. Due to this
erratum, further interrupts may still occur.
Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this
erratum with any commercially available software.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
Software should be written to handle spurious VT-d fault interrupts.
Status:
HSM42.
HSM43.
Problem:
N/A. Erratum has been removed
AVX Gather Instruction That Causes a Fault or VM Exit May Incorrectly
Modify Its Destination Register
An execution of a 128-bit AVX gather instruction zeroes the upper 128 bits of the
instruction's destination register unless access to the first unmasked element causes a
fault or VM exit. Due to this erratum, these bits may be cleared even when accessing
the first unmasked element causes a fault or VM exit. Instructions impacted by this
erratum are: VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD,
VPGATHERDD, VPGATHERDQ, VPGATHERQD, and VPGATHERQQ.
Software that depends on the destination register of a 128-bit AVX gather instruction to
remain unchanged after access of the first unmasked element results in fault or VM exit
may not behave as expected.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
HSM44.
Problem:
Inconsistent NaN Propagation May Occur When Executing (V)DPPS
Instruction
Upon completion of the (V)DPPS instruction with multiple different NaN encodings in
the input elements, software may observe different NaN encodings in the destination
elements.
Inconsistent NaN encodings in the destination elements for the (V) DPPS instruction
may be observed.
For the steppings affected, see the
Summary Table of Changes.
Implication:
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
Specification Update
31
