K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
SYNCHRONOUS BURST OPERATION TERMINOLOGY
WAIT Control(WAIT)
UtRAM
The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity
can be programmed to be either low enable or high enable.
For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle.
Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable)
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV
Latency 5
CS
Read
Data out
WAIT
Write
Data in
WAIT
DQ0
DQ1
DQ2
DQ3
High-Z
Latency 5
D0
D1
D2
D3
High-Z
Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the
burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence
table in next page.
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Revision 1.0
January 2005
