K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.20 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)
(MRS=V
IH,
OE=V
IH
, WAIT=High-Z, UB & LB Controlled)
0
CLK
t
ADV
ADV
Address
CS
t
AS(A)
t
AH(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
t
CSS(A)
t
CW
t
AW
t
BW
UB, LB
t
AS
WE
t
WLRL
t
WP
t
DW
t
DH
Data in
Read Latency 5
Data out
High-Z
Data Valid
High-Z
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when
CS goes or and WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
AW
is measured from the address valid to the end of write. In this address latch type write timing, t
WC
is same as t
AW.
3. t
CW
is measured from the CS going low to the end of write.
4. t
BW
is measured from the UB and LB going low to the end of write.
5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 24. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS
(Address Latch Type, UB & LB Controlled)
Symbol
Min
t
ADV
t
AS(A)
t
AH(A)
t
CSS(A)
t
CW
t
AW
7
0
7
10
60
60
Speed
Max
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
t
BW
t
WP
t
WLRL
t
AS
t
DW
t
DH
Units
Symbol
Min
60
55
1)
1
0
30
0
Speed
Max
-
-
-
-
-
-
ns
ns
clock
ns
ns
ns
Units
1. t
WP
(min)=70ns for continuous write operation over 50 times.
- 26 -
Revision 1.0
January 2005
