K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4]
(MRS=V
IH
)
0
T
CLK
t
ADVS
ADV
t
AS(B)
Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
t
ADVH
t
BEADV
t
AH(B)
Don’t Care
t
AS(B)
Valid
t
AH(B)
t
CSS(B)
CS
t
WES
t
WEH
WE
t
BC
t
CSS(B)
t
BC
t
OEL
OE
t
BS
t
BH
LB, UB
Latency 5
Data in
D0
D1
D2
t
BEL
t
DS
t
DHC
D3
High-Z
Latency 5
t
CD
t
OH
DQ0 DQ1 DQ2 DQ3
t
HZ
Data out
t
WL
WAIT
High-Z
t
WH
High-Z
t
WZ
t
WL
t
WH
(SYNCHRONOUS BURST READ & WRITE CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS
Symbol
Min
t
BEADV
7
Speed
Max
-
ns
Units
Symbol
Min
Speed
Max
Units
- 45 -
Revision 1.0
January 2005
