K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
UtRAM
Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2)
[Latency=5,Burst Length=4,WP=Low enable](OE=V
IH
, MRS=V
IH
)
- CS Low Holding Consecutive Burst Write
0
T
CLK
t
ADVH
t
ADVS
ADV
t
BEADV
t
AS(B)
Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
t
AH(B)
Don’t Care
Valid
t
CSS(B)
CS
t
BC
t
BS
t
BH
t
BMS
t
BMH
LB, UB
t
WEH
WE
t
WES
t
DS
Latency 5
Data in
t
WL
WAIT
High-Z
t
WH
t
DHC
D0
D1
D2
t
DHC
D3
t
AWL
t
WH
Latency 5
D0
t
WHP
(SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
4. D2 is masked by UB and LB.
5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
6. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 34. BURST WRITE AC CHARACTERISTICS
(CS Low Holding Consecutive Burst)
Symbol
Min
t
BS
t
BH
t
BMS
t
BMH
t
WES
t
WEH
5
5
7
7
5
5
Speed
Max
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
t
WHP
t
DS
t
DHC
t
WL
t
AWL
t
WH
Units
Symbol
Min
5
5
3
-
-
-
Speed
Max
-
-
-
10
10
12
ns
ns
ns
ns
ns
ns
Units
- 36 -
∼
∼
Revision 1.0
January 2005
