K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
ASYNCHRONOUS WRITE TIMING WAVEFORM
Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)
(MRS=V
IH,
OE=V
IH
, WAIT=High-Z, UB & LB Controlled)
t
WC
Address
t
CW
CS
t
AW
t
BW
UB, LB
t
AS
t
WP
WE
t
DW
Data in
Data Valid
t
DH
t
WR
UtRAM
Data out
High-Z
High-Z
(ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high or WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS or WE going high.
5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS
(UB & LB Controlled)
Symbol
Min
t
WC
t
CW
t
AW
t
BW
t
WP
70
60
60
60
55
1)
Speed
Max
-
-
-
-
-
ns
ns
ns
ns
ns
t
AS
t
WR
t
DW
t
DH
Units
Symbol
Min
0
0
30
0
Speed
Max
-
-
-
-
ns
ns
ns
ns
Units
1. t
WP
(min)=70ns for continuous write operation over 50 times.
- 24 -
Revision 1.0
January 2005
