K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
SYNCHRONOUS BURST READ TIMING WAVEFORM
UtRAM
Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3)
[Latency=5,Burst Length=4,WP=Low enable](WE=V
IH
, MRS=V
IH
)
- Last Data Sustaining
0
T
CLK
t
ADVH
t
ADVS
ADV
t
AS(B)
Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
t
AH(B)
Don’t Care
t
CSS(B)
CS
t
BEL
LB, UB
t
BLZ
t
OEL
OE
t
OLZ
Latency 5
Data out
t
WL
WAIT
High-Z
t
BC
t
CD
Undefined
t
OH
DQ0
DQ1
DQ2
DQ3
t
WH
(SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining)
1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 32. BURST READ AC CHARACTERISTICS
(Last Data Sustaining)
Symbol
Min
t
BEL
t
OEL
t
BLZ
t
OLZ
1
1
5
5
Speed
Max
-
-
-
-
clock
clock
ns
ns
t
CD
t
OH
t
WL
t
WH
Units
Symbol
Min
-
3
-
-
Speed
Max
10
-
10
12
ns
ns
ns
ns
Units
- 34 -
Revision 1.0
January 2005
