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K1B6416B6C

K1B6416B6C

Model K1B6416B6C
Description 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
PDF file Total 46 pages (File size: 769K)
Chip Manufacturer SAMSUNG
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM
[Latency=5, Burst Length=4]
(MRS=V
IH
)
1
T
CLK
t
ADVS
ADV
t
AH(B)
Don’t Care
UtRAM
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
t
ADVH
t
BEADV
t
AS(B)
Address
Valid
Valid Address
t
CSS(B)
CS
t
BC
t
AW
t
CW
t
WLRL
t
WR
t
WP
WE
t
OEL
OE
t
BEL
LB, UB
t
AS
t
BW
t
DW
Data in
Latency 5
Data out
High-Z
t
WL
t
WH
WAIT
High-Z
High-Z
Read Latency 5
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
t
DH
Data Valid
t
CD
t
OH
DQ0 DQ1 DQ2 DQ3
t
HZ
High-Z
t
WZ
(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS
Symbol
Min
t
BEADV
7
Speed
Max
-
ns
t
WLRL
Units
Symbol
Min
1
Speed
Max
-
clock
Units
- 41 -
Revision 1.0
January 2005
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