K1B6416B6C
| Model | K1B6416B6C |
| Description | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| PDF file | Total 46 pages (File size: 769K) |
| Chip Manufacturer | SAMSUNG |
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4]
(MRS=V
IH
)
0
CLK
t
ADHP
ADV
t
WC
Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
T
12
13
14
15
16
17
18
19
20
t
ADVS
t
ADVH
t
AH(B)
t
AS(B)
Valid
Don’t Care
t
AW
t
CW
CS
t
WLRL
t
WP
WE
t
AS
t
WR
t
CSS(B)
t
BC
t
OEL
OE
t
BW
LB, UB
t
DW
Data in
t
DH
t
BEL
Data Valid
Latency 5
t
CD
t
OH
DQ0 DQ1 DQ2 DQ3
t
HZ
Data out
High-Z
t
WL
t
WH
t
WZ
WAIT
High-Z
Read Latency 5
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS
Symbol
Min
t
WLRL
1
Speed
Max
-
clock
t
ADHP
Units
Symbol
Min
5
Speed
Max
-
ns
Units
- 43 -
Revision 1.0
January 2005
