G1-233P-85-1.8
| Model | G1-233P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
8.2.1.2 CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction
returns the processor type, family, model, and stepping
information of the current processor in the EAX register
(see Table 8-18). The EBX and ECX registers are
reserved.
Table 8-19. EDX CPUID Data Returned
when EAX = 1 (Continued)
Returned
EDX
EDX[12]
EDX[13]
EDX[14]
EDX[15]
EDX[16]
EDX[22:17]
EDX[23]
EDX[24]
EDX[31:25]
1.
Content
1
0
0
0
1
0
0
1
0
0
Feature Flag
Memory Type Range
Registers
Page Global Enable
Machine Check
Architecture
Conditional Move
Instructions
Page Attribute Table
Reserved
MMX Instructions
Fast FPU Save and
Restore
Reserved
CR4
Bit
-
-
-
-
-
-
-
-
-
Table 8-18. EAX, EBX, ECX CPUID Data Returned
when EAX = 1
Register
EAX[3:0]
EAX[7:4]
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX
ECX
Returned
Contents
xx
4
5
0
-
-
-
Description
Stepping ID
Model
Family
Type
Reserved
Reserved
Reserved
0 = Not Supported
The standard feature flags supported are returned in the
EDX register as shown in Table 8-19. Each flag refers to a
specific feature and indicates if that feature is present on
the processor. Some of these features have protection con-
trol in CR4. Before using any of these features on the pro-
cessor, the software should check the corresponding
feature flag. Attempting to execute an unavailable feature
can cause exceptions and unexpected behavior. For exam-
ple, software must check EDX bit 4 before attempting to
use the Time Stamp Counter instruction.
8.2.1.3 CPUID Instruction with EAX = 00000002h
Standard function 02h (EAX = 02h) of the CPUID instruc-
tion returns information that is specific to the National
Semiconductor family of processors. Information about the
TLB is returned in EAX as shown in Table 8-20. Information
about the L1 cache is returned in EDX.
Table 8-20. Standard CPUID with
EAX = 00000002h
Register
EAX
Returned
Contents
xx xx 70 xxh
xx xx xx 01h
Description
TLB is 32 entry, 4-way set asso-
ciative, and has 4 KB pages.
The CPUID instruction needs to
be executed only once with an
input value of 02h to retrieve com-
plete information about the cache
and TLB.
Reserved
Reserved
xx xx xx 80h
L1 cache is 16 KB, 4-way set
associated, and has 16 bytes per
line.
Table 8-19. EDX CPUID Data Returned
when EAX = 1
Returned
EDX
EDX[0]
EDX[1]
EDX[2]
EDX[3]
EDX[4]
EDX[5]
EDX[6]
EDX[7]
EDX[8]
EDX[9]
EDX[10]
EDX[11]
Content
1
0
0
0
1
1
0
0
1
0
0
0
1
Feature Flag
FPU On-Chip
Virtual Mode Extension
Debug Extensions
Page Size Extensions
Time Stamp Counter
RDMSR / WRMSR
Instructions
Physical Address
Extensions
Machine Check Excep-
tion
CMPXCHG8B Instruction
On-Chip APIC Hardware
Reserved
SYSENTER / SYSEXIT
Instructions
CR4
Bit
-
-
-
-
2
-
-
-
-
-
-
-
EAX
EBX
ECX
EDX
Revision 1.0
219
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