G1-233P-85-1.8
| Model | G1-233P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
Table 8-31. MMX Instruction Set Summary (Continued)
MMX Instructions
PSRAW
Packed Shift Right Arithmetic Word
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by Immediate
PSRLD
Packed Shift Right Logical Dword
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by Immediate
PSRLQ
Packed Shift Right Logical Qword
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by Immediate
PSRLW
Packed Shift Right Logical Word
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by Immediate
PSUBB
Subtract Byte With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
PSUBD
Subtract Dword With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FFA [11 mm1 mm2] MMX reg 1 [dword] <---- MMX reg 1 [dword] subtract MMX reg 2 [dword]
0FFA [mod mm r/m]
MMX reg [dword] <---- MMX reg [dword] subtract memory [dword]
1/1
1/1
0FF8 [11 mm1 mm2]
0FF8 [mod mm r/m]
MMX reg 1 [byte] <---- MMX reg 1 [byte] subtract MMX reg 2 [byte]
MMX reg [byte] <---- MMX reg [byte] subtract memory [byte]
1/1
1/1
0FD1 [11 mm1 mm2] MMX reg 1 [word] <--shift right, shifting in zeroes by MMX reg 2 [word]
0FD1 [mod mm r/m]
0F71 [11 010 mm] #
MMX reg [word] <--shift right, shifting in zeroes by memory[word]
MMX reg [word] <--shift right, shifting in zeroes by imm[word]
1/1
1/1
1/1
0FD3 [11 mm1 mm2] MMX reg 1 [qword] <--shift right, shifting in zeroes by MMX reg 2 [qword]
0FD3 [mod mm r/m]
0F73 [11 010 mm] #
MMX reg [qword] <--shift right, shifting in zeroes by memory[qword]
MMX reg [qword] <--shift right, shifting in zeroes by [im byte]
1/1
1/1
1/1
0FD2 [11 mm1 mm2] MMX reg 1 [dword] <--shift right, shifting in zeroes by MMX reg 2 [dword]--
0FD2 [mod mm r/m]
0F72 [11 010 mm] #
MMX reg [dword] <--shift right, shifting in zeroes by memory[dword]--
MMX reg [dword] <--shift right, shifting in zeroes by [im byte]--
1/1
1/1
1/1
0FE1 [11 mm1 mm2] MMX reg 1 [word] <--arith shift right, shifting in zeroes by MMX reg 2 [word]--
0FE1 [mod mm r/m]
0F71 [11 100 mm] #
MMX reg [word] <--arith shift right, shifting in zeroes by memory[word--]
MMX reg [word] <--arith shift right, shifting in zeroes by [im byte]--
1/1
1/1
1/1
Opcode
Operation and Clock Count (Latency/Throughput)
PSUBSB
Subtract Byte Signed With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FE8 [11 mm1 mm2] MMX reg 1 [sign byte] <--sat-- MMX reg 1 [sign byte] subtract MMX reg 2 [sign
byte]
0FE8 [mod mm r/m]
MMX reg [sign byte] <--sat-- MMX reg [sign byte] subtract memory [sign byte]
1/1
1/1
PSUBSW
Subtract Word Signed With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FE9 [11 mm1 mm2] MMX reg 1 [sign word] <--sat-- MMX reg 1 [sign word] subtract MMX reg 2 [sign
word]
0FE9 [mod mm r/m]
MMX reg [sign word] <--sat-- MMX reg [sign word] subtract memory [sign word]
1/1
1/1
PSUBUSB
Subtract Byte Unsigned With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FD8 [11 mm1 mm2] MMX reg 1 [byte] <--sat-- MMX reg 1 [byte] subtract MMX reg 2 [byte]
0FD8 [11 mm reg]
MMX reg [byte] <--sat-- MMX reg [byte] subtract memory [byte]
1/1
1/1
PSUBUSW
Subtract Word Unsigned With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
PSUBW
Subtract Word With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FF9 [11 mm1 mm2]
0FF9 [mod mm r/m]
MMX reg 1 [word] <---- MMX reg 1 [word] subtract MMX reg 2 [word]
MMX reg [word] <---- MMX reg [word] subtract memory [word]
1/1
1/1
0FD9 [11 mm1 mm2] MMX reg 1 [word] <--sat-- MMX reg 1 [word] subtract MMX reg 2 [word]
0FD9 [11 mm reg]
MMX reg [word] <--sat-- MMX reg [word] subtract memory [word]
1/1
1/1
PUNPCKHBW
Unpack High Packed Byte, Data to Packed Words
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F68 [11 mm1 mm2]
0F68 [11 mm reg]
MMX reg 1 [byte] <--interleave-- MMX reg 1 [up byte], MMX reg 2 [up byte]
MMX reg [byte] <--interleave-- memory [up byte], MMX reg [up byte]
1/1
1/1
PUNPCKHDQ
Unpack High Packed Dword, Data to Qword
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F6A [11 mm1 mm2] MMX reg 1 [dword] <--interleave-- MMX reg 1 [up dword], MMX reg 2 [up dword]
0F6A [11 mm reg]
MMX reg [dword] <--interleave-- memory [up dword], MMX reg [up dword]
1/1
1/1
PUNPCKHWD
Unpack High Packed Word, Data to Packed Dwords
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F69 [11 mm1 mm2]
0F69 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [up word], MMX reg 2 [up word]
MMX reg [word] <--interleave-- memory [up word], MMX reg [up word]
1/1
1/1
PUNPCKLBW
Unpack Low Packed Byte, Data to Packed Words
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F60 [11 mm1 mm2]
0F60 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [low byte], MMX reg 2 [low byte]
MMX reg [word] <--interleave-- memory [low byte], MMX reg [low byte]
1/1
1/1
PUNPCKLDQ
Unpack Low Packed Dword, Data to Qword
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F62 [11 mm1 mm2]
0F62 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [low dword], MMX reg 2 [low
dword]
MMX reg [word] <--interleave-- memory [low dword], MMX reg [low dword]
1/1
1/1
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