G1-233P-85-1.8
| Model | G1-233P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Signal Definitions
(Continued)
2.2.4
Video Interface Signals (Continued)
BGA
Pin No
L2
SPGA
Pin No
R4
Type
O
Description
Flat Panel Horizontal Sync
Flat Panel Horizontal Sync establishes the line rate and horizon-
tal retrace interval for a TFT display. Polarity is programmable.
(See Table 4-31 on Page 151 for programming information.)
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal is not connected.
FP_VSYNC
J1
P2
O
Flat Panel Vertical Sync
Flat Panel Vertical Sync establishes the screen refresh rate and
vertical retrace interval for a TFT display. Polarity is programma-
ble. (See Table 4-31 on Page 152 for programming information.)
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal is not connected.
ENA_DISP
AD5
AM6
O
Display Enable
Display Enable indicates the active display portion of a scan line
to the CS5530.
In a CS5530-based system, this signal is required to be con-
nected.
VID_RDY
AD1
AK2
I
Video Ready
This input signal indicates that the video FIFO in the CS5530 is
ready to receive more data.
VID_VAL
M2
S3
O
Video Valid
VID_VAL indicates that video data to the CS5530 is valid.
VID_DATA[7:0]
Refer
Refer
to
to
Refer
Refer
to
to
O
Video Data Bus
When the Video Port is enabled, this bus drives Video (YUV or
RGB 5:6:5) data synchronous to the VID_CLK output.
O
Graphics Pixel Data Bus
This bus drives graphics pixel data synchronous to the PCLK
output.
Signal Name
FP_HSYNC
PIXEL[17:0]
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