G1-233P-85-1.8
| Model | G1-233P-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.11 FLOATING POINT UNIT OPERATIONS
The GX1 processor contains an FPU that is x87 and MMX
instruction-set compatible and adheres to the IEEE-754
standard. Because most applications that contain FPU
instructions intermix with integer instructions, the GX1 pro-
cessor’s FPU achieves high performance by completing
integer and FPU operations in parallel.
3.11.1 FPU Register Set
The FPU provides the user eight data registers, a control
register, and a status register. The CPU also provides a
data register tag word that improves context switching and
stack performance by maintaining empty/non-empty status
for each of the eight data registers. Two additional, regis-
ters contain pointers to (a) the memory location containing
the current instruction word and (b) the memory location
containing the operand associated with the current instruc-
tion word (if any).
3.11.2 FPU Tag Word Register
The FPU maintains a tag word register that is divided into
eight tag word fields. These fields assume one of four val-
ues depending on the contents of their associated data
registers: Valid (00), Zero (01), Special (10), and Empty
(11). Note: Denormal, Infinity, QNaN, SNaN and unsup-
ported formats are tagged as “Special” Tag values are
.
maintained transparently by the CPU and are only available
to the programmer indirectly through the FSTENV and
FSAVE instructions. The tag word with TAG fields for each
associated physical register, TAG(n), is shown in Table 3-38
3.11.3 FPU Status Register
The FPU communicates status information and operation
results to the CPU through the FPU status register, whose
fields are detailed in Table 3-38. These fields include infor-
mation related to exception status, operation execution sta-
tus, register status, operand class, and comparison results.
This register is continuously accessible to the CPU regard-
less of the state of the Control or Execution Units.
3.11.4 FPU Mode Control Register
The FPU Mode Control register, shown in Table 3-38, is
used by the GX1 processor to specify the operating mode
of the FPU. The register fields include information related
to the rounding mode selected, the amount of precision to
be used in the calculations, and the exception conditions
which should be reported to the GX1 processor using
traps. The user controls precision, rounding, and exception
reporting by setting or clearing appropriate bits.
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