G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
4.3.6
Memory Cycles
SDRAM Read Cycle
assumes that a previous ACT command has presented the
row address for the read operation. Note that the burst
length for the READ command is always two.
Figures 4-5 through 4-8 illustrate various memory cycles
that the memory controller supports. The following subsec-
tions describe some of the supported cycles.
SDCLK
CS#
RAS#
CAS#
WE#
MA
COL n
DQM
MD
n
n+1
Figure 4-5. Basic Read Cycle with a CAS Latency of Two
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