G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
8.1.2.3 s Field (Immediate Data Field Size)
When used, the 1-bit s field determines the size of the
immediate data field. If the s bit is set, the immediate field
of the opcode is 8 bits wide and is sign-extended to match
the operand size of the opcode. See Table 8-6.
8.1.3 mod and r/m Byte (Memory Addressing)
The mod and r/m fields within the mod r/m byte, select the
type of memory addressing to be used. Some instructions
use a fixed addressing mode (e.g., PUSH or POP) and
therefore, these fields are not present. Table 8-8 lists the
addressing method when 16-bit addressing is used and a
mod r/m byte is present. Some mod r/m field encodings are
dependent on the w field and are shown in Table 8-9.
Table 8-6. s Field Encoding
Immediate Field Size
8-Bit
Operand
Size
8 bits
8 bits
s
Field
0 (or not
present)
1
16-Bit
Operand Size
16 bits
8 bits
(sign-
extended)
32-Bit
Operand Size
32 bits
8 bits
(sign-
extended)
mod
Field
00
00
Table 8-8. mod r/m Field Encoding
16-Bit Address
Mode with
mod r/m Byte
1
DS:[BX+SI]
DS:[BX+DI]
SS:[BP+SI]
SS:[BP+DI]
DS:[SI]
DS:[DI]
DS:[d16]
DS:[BX]
32-Bit Address
Mode with mod r/m
Byte and No s-i-b
Byte Present
DS:[EAX]
DS:[ECX]
DS:[EDX]
DS:[EBX]
s-i-b is present
(See Table 8-15)
DS:[d32]
DS:[ESI]
DS:[EDI]
r/m
Field
000
001
010
011
100
101
110
111
8.1.2.4
eee Field (MOV-Instruction Register
Selection)
The eee field (bits [5:3]) is used to select the control, debug
and test registers in the MOV instructions. The type of reg-
ister and base registers selected by the eee field are listed
in Table 8-7. The values shown in Table 8-7 are the only valid
encodings for the eee bits.
00
00
00
00
00
00
Table 8-7. eee Field Encoding
eee Field
000
010
011
100
000
001
010
011
110
111
011
100
101
110
111
Register Type
Control Register
Control Register
Control Register
Control Register
Debug Register
Debug Register
Debug Register
Debug Register
Debug Register
Debug Register
Test Register
Test Register
Test Register
Test Register
Test Register
Base Register
CR0
CR2
CR3
CR4
DR0
DR1
DR2
DR3
DR6
DR7
TR3
TR4
TR5
TR6
TR7
10
10
10
101
110
111
DS:[DI+d16]
SS:[BP+d16]
DS:[BX+d16]
10
10
10
10
10
000
001
010
011
100
DS:[BX+SI+d16]
DS:[BX+DI+d16]
SS:[BP+SI+d16]
SS:[BP+DI+d16]
DS:[SI+d16]
DS:[EAX+d32]
DS:[ECX+d32]
DS:[EDX+d32]
DS:[EBX+d32]
s-i-b is present
(See Table 8-15)
SS:[EBP+d32]
DS:[ESI+d32]
DS:[EDI+d32]
01
01
01
01
01
01
01
01
000
001
010
011
100
101
110
111
DS:[BX+SI+d8]
DS:[BX+DI+d8]
SS:[BP+SI+d8]
SS:[BP+DI+d8]
DS:[SI+d8]
DS:[DI+d8]
SS:[BP+d8]
DS:[BX+d8]
DS:[EAX+d8]
DS:[ECX+d8]
DS:[EDX+d8]
DS:[EBX+d8]
s-i-b is present
(See Table 8-15)
SS:[EBP+d8]
DS:[ESI+d8]
DS:[EDI+d8]
11
1.
xxx
See Table 8-9.
See Table 8-9
d8 refers to 8-bit displacement, d16 refers to 16-bit displace-
ment, and d32 refers to a 32-bit displacement.
Revision 1.0
215
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