G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.6.3 Interrupt Vectors
When the CPU services an interrupt or exception, the cur-
rent program’s instruction pointer and flags are pushed
onto the stack to allow resumption of execution of the inter-
rupted program. In protected mode, the processor also
saves an error code for some exceptions. Program control
is then transferred to the interrupt handler (also called the
interrupt service routine). Upon execution of an IRET at the
end of the service routine, program execution resumes at
the instruction pointer address saved on the stack when the
interrupt was serviced.
3.6.3.1 Interrupt Vector Assignments
Each interrupt (except SMI#) and exception are assigned
one of 256 interrupt vector numbers as shown in Table 3-
reserved. INT instructions acting as software interrupts
may use any of interrupt vectors, 0 through 255.
The non-maskable hardware interrupt (NMI) is assigned
vector 2. Illegal opcodes including faulty FPU instructions
will cause an illegal opcode exception, interrupt vector 6.
NMI interrupts are enabled by setting bit 2 of the CCR7
register (Index EBh[2] = 1, see Table 3-11 on page 52 for
register format).
In response to a maskable hardware interrupt (INTR), the
CPU issues interrupt acknowledge bus cycles used to read
the vector number from external hardware. These vectors
should be in the range 32 to 255 as vectors 0 to 31 are pre-
defined.
3.6.3.2 Interrupt Descriptor Table
The interrupt vector number is used by the CPU to locate
an entry in the interrupt descriptor table (IDT). In real
mode, each IDT entry consists of a 4-byte far pointer to the
beginning of the corresponding interrupt service routine. In
protected mode, each IDT entry is an 8-byte descriptor.
The Interrupt Descriptor Table Register (IDTR) specifies
the beginning address and limit of the IDT. Following
RESET, the IDTR contains a base address of 00000000h
with a limit of 3FFh.
The IDT can be located anywhere in physical memory as
determined by the IDTR register. The IDT may contain dif-
ferent types of descriptors: interrupt gates, trap gates and
task gates. Interrupt gates are used primarily to enter a
hardware interrupt handler. Trap gates are generally used
to enter an exception handler or software interrupt handler.
If an interrupt gate is used, the Interrupt Enable Flag (IF) in
the EFLAGS register is cleared before the interrupt handler
is entered. Task gates are used to make the transition to a
new task.
Table 3-29. Interrupt Vector Assignments
Interrupt
Vector
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18:31
32:55
0:255
Function
Divide error
Debug exception
NMI interrupt
Breakpoint
Interrupt on overflow
BOUND range exceeded
Invalid opcode
Device not available
Double fault
Reserved
Invalid TSS
Segment not present
Stack fault
General protection fault
Page fault
Reserved
FPU error
Alignment check exception
Reserved
Maskable hardware interrupts
Programmed interrupt
Exception
Type
Fault
Trap/Fault
1
---
Trap
Trap
Fault
Fault
Fault
Abort
---
Fault
Fault
Fault
Trap/Fault
Fault
---
Fault
Fault
---
Trap
Trap
1.
Data breakpoints and single steps are traps. All other debug
exceptions are faults.
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