G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
4.0
Integrated Functions
chip count, small footprint designs. Performance degrada-
tion in traditional UMA systems is reduced through the use
of National Semiconductor’s Display Compression Technol-
ogy (DCT) architecture.
processor and how the internal bus interface unit operates
as the interface between the processor’s core units and the
integrated functions.
This section details how the integrated functions and inter-
nal bus interface unit operate and their respective registers.
The integrated functions in the Geode GX1 processor are:
•
Internal bus interface
•
SDRAM memory controller
•
High-performance 2D graphics accelerator
•
Display controller with separate CRT and TFT data
paths
•
PCI bridge
The design organizes the memory controller, graphics
pipeline and display controller into a Unified Memory Archi-
tecture (UMA). UMA simplifies system designs and signifi-
cantly reduces overall system costs associated with high
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
FPU
Internal Bus Interface Unit
X-Bus
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
PCI Bus
Figure 4-1. Internal Block Diagram
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Revision 1.0
