G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-31. Display Controller Timing Registers (Continued)
Bit
Name
Description
DC_V_TIMING_3 Register (R/W) (Locked)
Reserved:
Set to 0.
Vertical Sync End:
The line at which the CRT vertical sync signal becomes inactive minus 1.
Reserved:
Set to 0.
Vertical Sync Start:
The line at which the CRT vertical sync signal becomes active minus 1. For
interlaced display, note that the vertical counter is incremented twice during each line and since there
are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one field and
at the end of a line for the subsequent field.
Default Value = xxxxxxxxh
GX_BASE+8348h-834Bh
31:27
26:16
15:11
10:0
RSVD
V_SYNC_END
RSVD
V_SYNC_START
Note:
These values are specified in lines.
DC_FP_V_TIMING Register (R/W) (Locked)
Reserved:
Set to 0.
Flat Panel Vertical Sync End:
The line at which the flat panel vertical sync signal becomes inactive
minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal sync prior
to being output to the panel.
Reserved:
Set to 0.
Flat Panel Vertical Sync Start:
The line at which the internal flat panel vertical sync signal becomes
active minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal
sync prior to being output to the panel.
Default Value = xxxxxxxxh
GX_BASE+834Ch-834Fh
31:27
26:16
RSVD
FP_V_SYNC
_END
RSVD
FP_VSYNC
_START
15:11
10:0
Note:
These values are specified in lines.
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