G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Signal Definitions
(Continued)
Index Corner
1
A
B
C
D
E
F
G
H
J
K
L
VCC2
VCC2
VCC2
VCC2
MD40
VSS
TCLK
NC
VSS
MD41
MD10
MD11
MD44
MD14
MD15
VSS
VCC3
MD47
CASA#
MD13
MD46
VSS
VSS
MD12
MD45
MD42
MD43
VCC2
MD9
VCC2
TDO
REQ1#
VSS
VCC3
AD30
REQ0#
VSS
AD31
AD29
AD28
TDI
VSS
VSS
MD6
VCC2
MD39
VSS
MD8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A
B
VCC3
MD35
MD36
MD5
MD37
MD38
MD7
TDP
VSS
TDN
VCC3
AD27
AD25
CBE3#
AD26
AD24
VSS
AD21
AD23
AD22
VSS
VCC2
AD19
VCC2
AD20
VCC2
AD16
VCC3
CBE2#
STOP#
SERR#
CBE1#
PAR
VSS
AD13
AD11
AD9
AD10
AD12
AD7
CBE0#
AD8
AD6
VSS
INTR
AD5
VCC3
AD3
AD4
TEST1
VSS
AD2
SMI#
AD0
VCC2
AD1
VCC2
TEST3
VCC2
MD0
VSS
TEST0
TEST2
MD33
MD1
MD32
MD3
MD4
VCC3
MD2
MD34
VSS
TRDY#
VSS
LOCK#
AD18
FRAME#
AD17
IRDY#
VSS
VCC3
AD14
VSS
IRQ13
C
D
E
F
G
H
J
K
L
M
PERR#
AD15
REQ2#
VCC2
DEVSEL#
VCC2
VSS
GNT0#
CKMD2
GNT2#
SUSPA#
VSS
TEST
GNT1#
M
RESET
SUSP#
TMS
N
VCC3
VCC3
N
P
FPVSYNC
SERIALP
CKMD1
VSS
P
Q
R
FPHSYNC
PIX0
S
T
CKMD0
VID_VAL
PIX1
PIX2
VCC3
PIX3
U
V
VSS
VSS
Geode™
GX1
Processor
320 SPGA - Top View
Q
R
S
T
U
V
VID_CLK
PIX5
PIX4
PIX9
VSS
PIX7
PIX10
PIX11
VSS
PIX13
VCC2
DCLK
VCC2
PIX16
PIX17
VDAT6
VDAT5
VSS
VDAT0
VDAT2
VSS
VCC2
MD31
VSS
MD29
VSS
MD59
MD28
MD26
MD60
MD27
MD58
MD25
VSS
MD57
MD56
VCC3
MD24
MD54
VSS
MD55
MD23
MD53
CKEB
MD22
MD21
VSS
MD51
VCC3
MD52
MD20
MD19
MD18
MD17
VSS
MD50
MD49
MD48
VCC2
VCC2
MD16
VCC2
VCC2
DQM3
DQM6
DQM7
VSS
DQM2
VSS
CS3#
VSS
MA10
VCC2
SYSCLK
WEA#
DQM0
DQM1
CS2#
VSS
CS0#
RASB#
VCC2
MA2
VCC2
MA4
VSS
MA8
BA1
VSS
CKEA
MA12
CS1#
VCC3
MA11
MA9
MA5
VSS
VSS
WEB#
W
X
PIX6
NC
W
X
CASB#
Y
PIX8
Y
DQM4
Z
NC
DQM5
Z
AA
VCC3
VCC3
AA
AB
PIX12
RASA#
AB
AC
VCC2
VCC2
MA0
VCC2
AC
AD
CRTHSYNC
AD
AE
PIX14
VSS
PIX15
MA1
AE
AF
MA3
AF
AG
VSS
VSS
AG
AH
CRTVSYNC
MA6
MA7
BA0
AH
PCLK
VRDY
FLT#
AJ
AK
AJ
AK
SDCLK0
SDCLK2
SDCLKIN
AL
VCC2
VDAT4
SDCLK1
VCC2
RWCLK
MD63
MD62
SDCLKOUT
MD61
VCC3
VCC3
NC
VSS
AL
VDAT7
VSS
VDAT3
ENDIS
SDCLK3
VSS
VCC2
MD30
AM
AN
AM
AN
VCC2
VDAT1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Note:
Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
(For order information, refer to Section A.1 “Order Information” on page 246.)
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Revision 1.0
