G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
Table 8-29. FPU Instruction Set Summary (Continued)
FPU Instruction
FNOP
No Operation
FPATAN
Function Eval: Tan-1(y/x)
FPREM
Floating Point Remainder
FPREM1
Floating Point Remainder IEEE
FPTAN
Function Eval: Tan(x)
FRNDINT
Round to Integer
FRSTOR
Load FPU Environment and Register
FSAVE
Save FPU Environment and Register
FNSAVE
Save FPU Environment and Register
FSCALE
Floating Multiply by 2n
FSIN
Function Evaluation: Sin(x)
FSINCOS
Function Eval.: Sin(x)& Cos(x)
D9 D0
D9 F3
D9 F8
D9 F5
D9 F2
D9 FC
DD [mod 100 r/m]
(9B)DD [mod 110 r/m]
DD [mod 110 r/m]
D9 FD
D9 FE
D9 FB
Opcode
No Operation
ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS
TOS <--- Rem[TOS / ST(1)]
TOS <--- Rem[TOS / ST(1)]
TOS <--- TAN(TOS); then push 1.0 onto stack
TOS <--- Round(TOS)
Restore state
Wait, then save state
Save state
TOS <--- TOS
×
2
(ST(1))
TOS <--- SIN(TOS)
temp <--- TOS;
TOS <--- SIN(temp); then
push COS(temp) onto stack
TOS <--- Square Root of TOS
Operation
Clock
Count
2
97 - 161
82 - 91
82 - 91
117 - 129
10 - 20
56 - 72
57 - 67
55 - 65
7 - 14
76 - 140
145 - 161
1
1
1
3
Issue
FSQRT
Floating Point Square Root
FST
Store FPU Register
Top of Stack
64-bit Real
32-bit Real
FSTP
Store FPU Register, Pop
Top of Stack
80-bit Real
64-bit Real
32-bit Real
FBSTP
Store BCD Data, Pop
FIST
Store Integer FPU Register
32-bit Integer
16-bit Integer
FISTP
Store Integer FPU Register, Pop
64-bit Integer
32-bit Integer
16-bit Integer
FSTCW
Store FPU Mode Control Register
FNSTCW
Store FPU Mode Control Register
FSTENV
Store FPU Environment
FNSTENV
Store FPU Environment
FSTSW
Store FPU Status Register
FNSTSW
Store FPU Status Register
FSTSW AX
Store FPU Status Register to AX
FNSTSW AX
Store FPU Status Register to AX
FSUB
Floating Point Subtract
Top of Stack
80-bit Register
64-bit Real
32-bit Real
FSUBP
Floating Point Subtract, Pop
FSUBR
Floating Point Subtract Reverse
Top of Stack
80-bit Register
64-bit Real
32-bit Real
D9 FA
59 - 60
DD [1101 0 n]
DD [mod 010 r/m]
D9 [mod 010 r/m]
ST(n) <--- TOS
M.DR <--- TOS
M.SR <--- TOS
2
2
2
DB [1101 1 n]
DB [mod 111 r/m]
DD [mod 011 r/m]
D9 [mod 011 r/m]
DF [mod 110 r/m]
ST(n) <--- TOS; then pop TOS
M.XR <--- TOS; then pop TOS
M.DR <--- TOS; then pop TOS
M.SR <--- TOS; then pop TOS
M.BCD <--- TOS; then pop TOS
2
2
2
2
57 - 63
DB [mod 010 r/m]
DF [mod 010 r/m]
M.SI <--- TOS
M.WI <--- TOS
8 - 13
7 - 10
DF [mod 111 r/m]
DB [mod 011 r/m]
DF [mod 011 r/m]
(9B)D9 [mod 111 r/m]
D9 [mod 111 r/m]
(9B)D9 [mod 110 r/m]
D9 [mod 110 r/m]
(9B)DD [mod 111 r/m]
DD [mod 111 r/m]
(9B)DF E0
DF E0
M.LI <--- TOS; then pop TOS
M.SI <--- TOS; then pop TOS
M.WI <--- TOS; then pop TOS
Wait Memory <--- Control Mode Register
Memory <--- Control Mode Register
Wait Memory <--- Env. Registers
Memory <--- Env. Registers
Wait Memory <--- Status Register
Memory <--- Status Register
Wait AX <--- Status Register
AX <--- Status Register
10 - 13
8 - 13
7 - 10
5
3
14 - 24
12 - 22
6
4
4
2
DC [1110 1 n]
D8 [1110 0 n]
DC [mod 100 r/m]
D8 [mod 100 r/m]
DE [1110 1 n]
ST(n) <--- ST(n) - TOS
TOS <--- TOS - ST(n
TOS <--- TOS - M.DR
TOS <--- TOS - M.SR
ST(n) <--- ST(n) - TOS; then pop TOS
4-9
4-9
4-9
4-9
4-9
DC [1110 0 n]
D8 [1110 1 n]
DC [mod 101 r/m]
D8 [mod 101 r/m]
TOS <--- ST(n) - TOS
ST(n) <--- TOS - ST(n)
TOS <--- M.DR - TOS
TOS <--- M.SR - TOS
4-9
4-9
4-9
4-9
Revision 1.0
237
www.national.com
