G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.3.2 System Register Set
The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level pro-
grammers who generate operating systems and memory
management programs. Associated with the System Reg-
ister Set are certain tables and segments which are listed
in Table 3-5.
The
Control Registers
control certain aspects of the GX1
processor such as paging, coprocessor functions, and seg-
ment protection.
The
Configuration Registers
are used to define the GX1
CPU setup including cache management.
The
Debug Registers
provide debugging facilities for the
GX1 processor and enable the use of data access break-
points and code execution breakpoints.
The
Test Registers
provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).
The
Descriptor Table Register
hold descriptors that man-
age memory segments and tables, interrupts and task
switching. The tables are defined by corresponding regis-
ters.
The two
Task State Segment Tables
defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
The
ID Registers
allow BIOS and other software to identify
the specific CPU and stepping.
System Management Mode (SMM) control information is
stored in the
SMM Registers.
and function.
Descriptor
Tables
Test
Registers
Configuration
Registers
Debug
Registers
Table 3-5. System Register Set
Group
Control
Registers
Name
CR0
CR2
CR3
CR4
CCRn
DR0
DR1
DR2
DR3
DR6
DR7
TR3
TR4
TR5
TR6
TR7
GDT
IDT
LDT
Descriptor
Table
Registers
Task State
Segment and
Registers
ID
Registers
SMM
Registers
GDTR
IDTR
LDTR
TSS
TR
DIRn
SMARn
SMHRn
Performance
Registers
PCR0
Function
System Control
Register
Page Fault Linear
Address Register
Page Directory Base
Register
Time Stamp Counter
Configuration Con-
trol Registers
Linear Breakpoint
Address 0
Linear Breakpoint
Address 1
Linear Breakpoint
Address 2
Linear Breakpoint
Address 3
Breakpoint Status
Breakpoint Control
Cache Test
Cache Test
Cache Test
TLB Test Control
TLB Test Data
General Descriptor
Table
Interrupt Descriptor
Table
Local Descriptor
Table
GDT Register
IDT Register
LDT Register
Task State Segment
Table
TSS Register Setup
Device Identification
Registers
SMM Address
Region Registers
SMM Header
Addresses
Performance Con-
trol Register
Width
(Bits)
32
32
32
32
8
32
32
32
32
32
32
32
32
32
32
32
32
32
16
32
32
16
16
16
8
8
8
8
Revision 1.0
47
www.national.com
