G1-266B-85-1.8
| Model | G1-266B-85-1.8 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-31. Display Controller Timing Registers (Continued)
Bit
Name
Description
DC_H_TIMING_3 Register (R/W) (Locked)
Reserved:
Set to 0.
Horizontal Sync End:
The character clock count at which the CRT horizontal sync signal becomes
inactive minus 1. The field [26:16] may be programmed with the pixel count minus 1, although bits
[18:16] are ignored. The sync end position is programmable on 8-pixel boundaries only.
Ignored
Reserved:
Set to 0.
Horizontal Sync Start:
The character clock count at which the CRT horizontal sync signal becomes
active minus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0]
are ignored. The sync start position is programmable on 8-pixel boundaries only.
Ignored
Default Value = xxxxxxxxh
GX_BASE+8338h-833Bh
31:27
26:19
RSVD
H_SYNC_END
18:16
15:11
10:3
IGRD
RSVD
H_SYNC_START
2:0
Note:
IGRD
This register should also be programmed appropriately for flat panel only display since the horizontal sync transition deter-
mines when to advance the vertical counter.
C_FP_H_TIMING Register (R/W) (Locked)
Reserved:
Set to 0.
Flat Panel Horizontal Sync End:
The pixel count at which the flat panel horizontal sync signal
becomes inactive minus 1.
Reserved:
Set to 0.
Flat Panel Horizontal Sync Start:
The pixel count at which the flat panel horizontal sync signal
becomes active minus 1.
Default Value = xxxxxxxxh
GX_BASE+833Ch-833Fh
31:27
26:16
15:11
10:0
Note:
RSVD
FP_H_SYNC
_END
RSVD
FP_H_SYNC
_START
These values are specified in pixels rather than character clocks to allow precise control over sync position. For flat panels
which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee that the
sync signal will meet proper setup and hold times.
DC_V_TIMING_1 Register (R/W) (Locked)
Reserved:
Set to 0.
Vertical Total:
The total number of lines for a given frame scan minus 1. The value is necessarily
greater than the V_ACTIVE field because it includes border lines and blanked lines. If the display is
interlaced, the total number of lines must be odd, so this value should be an even number.
Reserved:
Set to 0.
Vertical Active:
The total number of lines for the displayed portion of a frame scan minus 1. For flat
panels, if this value is less than the panel active vertical resolution (V_PANEL), the parameters
V_BLANK_START, V_BLANK_END, V_SYNC_START, and V_SYNC_END should be reduced by the
following value (V_ADJUST) to achieve vertical centering: V_ADJUST = (V_PANEL – V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value should be an odd
number.
Default Value = xxxxxxxxh
GX_BASE+8340h-8343h
31:27
26:16
RSVD
V_TOTAL
15:11
10:0
RSVD
V_ACTIVE
Note:
These values are specified in lines.
DC_V_TIMING_2 Register (R/W) (Locked)
Reserved:
Set to 0.
Vertical Blank End:
The line at which the vertical blanking signal becomes inactive minus 1. If the
display is interlaced, no border is supported, so this value should be identical to V_TOTAL.
Reserved:
Set to 0.
Vertical Blank Start:
The line at which the vertical blanking signal becomes active minus 1. If the
display is interlaced, this value should be programmed to V_ACTIVE plus 1.
Default Value = xxxxxxxxh
GX_BASE+8344h-8347h
31:27
26:16
15:11
10:0
Note:
RSVD
V_BLANK_END
RSVD
V_BLANK_
START
These values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/active
timing.
Revision 1.0
151
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