G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
4.3.3
SDRAM Commands
MRS
— The Mode Register Set command defines the spe-
cific mode of operation of the SDRAM. This definition
includes the selection of burst length, burst type, and CAS
latency. CAS latency is the delay, in clock cycles, between
the registration of a read command and the availability of
the first piece of output data.
The burst length is programmed by address bits MA[2:0],
the burst type by address bit MA3 and the CAS latency by
address bits MA[6:4].
The memory controller only supports a burst length of two
and burst type of interleave.
The field value on MA[12:0] and BA[1:0] during the MRS
cycle are as shown in Table 4-13.
PRE
— The precharge command is used to deactivate the
open row in a particular component bank or the open row
in all (2 or 4, device dependent) component banks.
Address pin MA10 determines whether one or all compo-
nent banks are to be precharged. In the case where only
one component bank is to be precharged, BA[1:0] selects
which bank. Once a component bank has been pre-
charged, it is in the Idle state and must be activated prior to
any read or write commands.
This subsection discusses the SDRAM commands sup-
ported by the memory controller. Table 4-12 summarizes
these commands followed by detailed operational informa-
tion regarding each command. Refer to the SDRAM manu-
facturer’s specification for more information on component
banks..
Table 4-12. Basic Command Truth Table
Name
MRS
PRE
ACT
WRT
Command
Mode Register Set
Bank Precharge
Bank activate/row-
address entry
Column address
entry/Write opera-
tion
Column address
entry/Read opera-
tion
Control input inhibit/
No operation
CBR Refresh or
Auto Refresh
CS
L
L
L
L
RAS
L
L
L
H
CAS
L
H
H
L
WE
L
L
H
L
READ
L
H
L
H
DESL
RFSH
1
1.
H
L
X
L
X
L
X
H
This command is CBR (CAS-before-RAS) refresh when CKE
is high and self refresh when CKE is low.
Table 4-13. Address Line Programming during MRS Cycles
BA[1:0]
00
MA[12:7]
000000
MA[6:4]
CAS Latency:
000 = Reserved
010 = 2 CLK
100 = 4 CLK
110 = 6 CLK
001 = 1 CLK
011 = 3 CLK
101 = 5 CLK
111 = 7 CLK
MA3
1
Burst type is always
interleave.
MA[2:0]
001
Burst length is always 2.
128-bit transfer.
www.national.com
110
Revision 1.0
