G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.6.4 Interrupt and Exception Priorities
As the CPU executes instructions, it follows a consistent
policy for prioritizing exceptions and hardware interrupts.
The priorities for competing interrupts and exceptions are
listed in Table 3-30. SMM interrupts always take prece-
dence. Debug traps for the previous instruction and next
instructions are handled as the next priority. When NMI and
maskable INTR interrupts are both detected at the same
instruction boundary, the GX1 processor services the NMI
interrupt first.
The CPU checks for exceptions in parallel with instruction
decoding and execution. Several exceptions can result
from a single instruction. However, only one exception is
generated upon each attempt to execute the instruction.
Each exception service routine should make the appropri-
ate corrections to the instruction and then restart the
instruction. In this way, exceptions can be serviced until the
instruction executes properly.
The CPU supports instruction restart after all faults, except
when an instruction causes a task switch to a task whose
Task State Segment (TSS) is partially not present. A TSS
can be partially not present if the TSS is not page aligned
and one of the pages where the TSS resides is not cur-
rently in memory.
Table 3-30. Interrupt and Exception Priorities
Priority
0
1
2
3
4
5
6
7
8
9
10
11
Reset.
SMM hardware interrupt.
Debug traps and faults from previous instruction.
Debug traps for next instruction.
Non-maskable hardware interrupt.
Maskable hardware interrupt.
Faults resulting from fetching the next instruction.
Faults resulting from instruction decoding.
WAIT instruction and TS = 1 and MP = 1.
ESC instruction and EM = 1 or TS = 1.
Floating point error exception.
Segmentation faults (for each memory reference
required by the instruction) that prevent transferring
the entire memory operand.
Page Faults that prevent transferring the entire
memory operand.
Alignment check fault.
Description
Notes
Caused by the assertion of RESET.
SMM interrupts are caused by SMI# asserted and always have high-
est priority.
Includes single-step trap and data breakpoints specified in the debug
registers.
Includes instruction execution breakpoints specified in the debug reg-
isters.
Caused by NMI asserted.
Caused by INTR asserted and IF = 1.
Includes segment not present, general protection fault and page fault.
Includes illegal opcode, instruction too long, or privilege violation.
Device not available exception generated.
Device not available exception generated.
Caused by unmasked floating point exception with NE = 1.
Includes segment not present, stack fault, and general protection
fault.
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