G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
Table 3-7. CR4-CR0 Bit Definitions (Continued)
Bit
Name
Description
Control Register 2 (R/W)
Page Fault Linear Address:
With paging enabled and after a page fault, PFLA contains the linear address of the
address that caused the page fault.
Control Register 1 (R/W)
Reserved
Control Register 0 (R/W)
Paging Enable Bit:
If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the state
of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change take effect.
Cache Disable:
If CD = 1, no further cache line fills occur. However, data already present in the cache continues to
be used if the requested address hits in the cache. Writes continue to update the cache and cache invalidations
due to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to completely
disable any cache activity.
Not Write-Through:
If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are
issued to the external bus only for a cache miss, a line replacement of a modified line, execution of a locked instruc-
tion, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-through mode. In
write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot be changed if
LOCK_NW = 1 in CCR2.
Reserved
Alignment Check Mask:
If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable align-
ment check faults. Setting AM = 0 prevents AC faults from occurring.
Reserved
Write Protect:
Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be writ-
ten from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.
Reserved
Numerics Exception:
NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions are
to be handled by external interrupts.
Reserved:
Do not attempt to modify, always 1.
Task Switched:
Set whenever a task switch operation is performed. Execution of a floating point instruction with
TS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.
Emulate Processor Extension:
If EM = 1, all floating point instructions cause a DNA fault 7.
Monitor Processor Extension:
If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA) fault
7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the state of the
MP bit. The MP bit should be set to one during normal operations.
Protected Mode Enable:
Enables the segment based protection mechanism. If PE = 1, protected mode is
enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to
CR2 Register
31:0
PFLA
CR1 Register
31:0
RSVD
CR0 Register
31
30
PG
CD
29
NW
28:19
18
17
16
15:6
5
4
3
2
1
RSVD
AM
RSVD
WP
RSVD
NE
RSVD
TS
EM
MP
0
PE
Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits
CR0[3:1]
TS
0
0
1
1
0
0
1
1
EM
0
0
0
0
1
1
1
1
MP
0
1
0
1
0
1
0
1
WAIT
Execute
Execute
Execute
Fault 7
Execute
Execute
Execute
Fault 7
Instruction Type
ESC
Execute
Execute
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Revision 1.0
49
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