G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Signal Definitions
(Continued)
2.1
PIN ASSIGNMENTS
Table 2-1. Pin Type Definitions
Mnemonic
I
I/O
O
OD
Definition
Standard input pin.
Bidirectional pin.
Totem-pole output.
Open-drain output structure that
allows multiple devices to share the
pin in a wired-OR configuration.
Pull-up resistor.
Pull-down resistor.
Sustained tri-state, an active-low tri-
state signal owned and driven by one
and only one agent at a time. The
agent that drives an s/t/s pin low
must drive it high for at least one
clock before letting it float. A new
agent cannot start driving an s/t/s
signal any sooner than one clock
after the previous owner lets it float.
A pull-up resistor on the motherboard
is required to sustain the inactive
state until another agent drives it.
Power pin.
Ground pin.
The "#" symbol at the end of a signal
name indicates that the active, or
asserted state occurs when the sig-
nal is at a low voltage level. When "#"
is not present after the signal name,
the signal is asserted when at a high
voltage level.
Tri-state signal.
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
by pin number and alphabetically by signal name, respec-
tively.
with Table 2-4 and Table 2-5 listing the pin assignments
sorted by pin number and alphabetically by signal name,
respectively.
In Section 2.2 “Signal Descriptions” on page 31 a descrip-
tion of each signal is provided within its associated func-
tional group.
PU
PD
s/t/s
VCC (PWR)
VSS (GND)
#
t/s
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