G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Electrical Specifications
(Continued)
Table 6-18. Video Interface Signals (Refer to Figures 6-11 through 6-13)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tcyc
Parameter
PCLK Period
PCLK High Time
PCLK Low Time
PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC,
FP_VSYNC, ENA_DISP Valid Delay from PCLK Rising Edge
VID_CLK Period
VID_RDY Setup to VID_CLK Rising Edge
VID_RDY Hold to VID_CLK Rising Edge
VID_VAL, VID_DATA[7:0] Valid Delay from VID_CLK Rising Edge
DCLK Period
DCLK Rise/Fall Time
DCLK Duty Cycle
40
Min
6.3
2.8
2.8
2
6.7
5
2
2
6.3
2
60
4
4
Max
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
t1
t2
t3
t4
PCLK
PIXEL[17:0],
CRT_HSYNC, CRT_VSYNC,
FP_HSYNC, FP_VSYNC,
ENA_DISP
Data Valid
Data Valid
Figure 6-11. Graphics Port Timing
Revision 1.0
203
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