G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.5.4 Paging Mechanism
The paging mechanism translates a linear address to its
corresponding physical address. If the required page is not
currently present in RAM, an exception is generated. When
the operating system services the exception, the required
page can be loaded into memory and the instruction
restarted. Pages are either 4 KB or 1 MB in size. The CPU
defaults to 4 KB pages that are aligned to 4 KB boundaries.
A page is addressed by using two levels of tables as illus-
trated in Figure 3-8. Bits [31:22] of the 32-bit linear
address, the Directory Table Index (DTI), are used to locate
an entry in the page directory table. The page directory
table acts as a 32-bit master index to up to 1 KB individual
second-level page tables. The selected entry in the page
directory table, referred to as the directory table entry
(DTE), identifies the starting address of the second-level
page table. The page directory table itself is a page and is
therefore aligned to a 4 KB boundary. The physical address
of the current page directory table is stored in the CR3 con-
Linear
Address
31
Directory Table Index
(DTI)
22 21
Page Table Index
(PTI)
12 11
Page Frame Offset
(PFO)
0
trol register, also referred to as the Page Directory Base
Register (PDBR).
Bits [21:12] of the 32-bit linear address, referred to as the
Page Table Index (PTI), locate a 32-bit entry in the second-
level page table. This page table entry (PTE) contains the
base address of the desired page frame. The second-level
page table addresses up to 1K individual page frames. A
second-level page table is 4 KB in size and is itself a page.
Bits [11:0] of the 32-bit linear address, the Page Frame Off-
set (PFO), locate the desired physical data within the page
frame.
Since the page directory table can point to 1 KB page
tables, and each page table can point to 1 KB page frames,
a total of 1 MB page frames can be implemented. Each
page frame contains 4 KB, therefore, up to 4 GB of virtual
memory can be addressed by the CPU with a single page
directory table.
4 GB
DTE Cache
2-Entry
Fully Associative
1
Main TLB
32-Entry
4-Way Set
Associative
31
0
0
-4 KB
4 KB
DTE
CR3
Control
Register
Directory Table
0
Page Table
PTE
4 KB
Physical Page
-0
0
Memory
External Memory
0
Figure 3-8. Paging Mechanism
Revision 1.0
77
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