G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Instruction
NOP
No Operation
NOT
Boolean Complement
OIO
Official Invalid Opcode
OR
Boolean OR
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
OUT
Output to Port
Fixed Port
Variable Port
OUTS
Output String
POP
Pop Value off Stack
Register/Memory
Register (short form)
Segment Register (ES, SS, DS)
Segment Register (FS, GS)
POPA
Pop All General Registers
POPF
Pop Stack into FLAGS
PREFIX BYTES
Assert Hardware LOCK Prefix
Address Size Prefix
Operand Size Prefix
Segment Override Prefix
-CS
-DS
-ES
-FS
-GS
-SS
PUSH
Push Value onto Stack
Register/Memory
Register (short form)
Segment Register (ES, CS, SS, DS)
Segment Register (FS, GS)
Immediate
PUSHA
Push All General Registers
PUSHF
Push FLAGS Register
RCL
Rotate Through Carry Left
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
RCR
Rotate Through Carry Right
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
RDMSR
Read Tmodel Specific Register
RDTSC
Read Time Stamp Counter
REP INS
Input String
REP LODS
Load String
REP MOVS
Move String
REP OUTS
Output String
REP STOS
Store String
D [000w] [mod 011 r/m]
D [001w] [mod 011 r/m]
C [000w] [mod 011 r/m] #
0F 32
0F 31
F3 6[110w]
F3 A[110w]
F3 A[010w]
F3 6[111w]
F3 A[101w]
x
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
-
-
-
-
-
-
-
17+4n
9+2n
12+2n
24+4n
9+2n
17+4n\
32+4n
9+2n
12+2n
24+4n\
39+4n
9+2n
b
b
b
b
b
h,m
h
h
h,m
h
4
8
8
4
8
8
b
h
u -
u -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D [000w] [mod 010 r/m]
D [001w] [mod 010 r/m]
C [000w] [mod 010 r/m] #
x
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
3
8
8
3
8
8
b
h
u -
u -
FF [mod 110 r/m]
5 [0 reg]
[000 sreg2 110]
0F [10 sreg3 000]
6 [10s0] ###
60
9C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1/3
1
1
1
1
11
2
1/3
1
1
1
1
11
2
b
b
h
h
b
h
F0
67
66
2E
3E
26
64
65
36
-
-
-
-
-
-
-
-
-
m
8F [mod 000 r/m]
5 [1 reg]
[000 sreg2 111]
0F [10 sreg3 001]
61
9D
-
x
-
x
-
x
-
x
-
x
-
x
-
x
-
x
-
x
-
-
-
-
-
-
-
-
-
1/4
1
1
1
9
8
1/4
1
6
6
9
8
b
b
h
h,n
b
h,i,j
E [011w] #
E [111w]
6 [111w]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
14
15
14/28
14/28
15/29
b
h,m
m
0 [10dw] [11 reg r/m]
0 [100w] [mod reg r/m]
0 [101w] [mod reg r/m]
8 [00sw] [mod 001 r/m] ###
0 [110w] ###
0 -
-
-
x
x
u x
0
1
1
1
1
1
1
1
1
1
1
b
h
90
F [011w] [mod 010 r/m]
0F FF
Opcode
O D I T S Z A P C
F F F F F F F F F
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
Clock Count
(Reg/Cache Hit)
1
1
1
1
1
8-125
b
Issues
h
0 -
Revision 1.0
229
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