G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
4.3.7
SDRAM Interface Clocking
The delay for SDCLKIN from SDCLKOUT must be
designed so that it lags the SDCLKs at the DRAM by
approximately 1 ns (check application notes for additional
information). The delay should also include the SDCLK
transmission line delay. All four SDCLK traces on the board
should be the same length, so there is no skew between
them. These guidelines allow the memory interface to
operate at a higher performance.
The GX1 processor drives the SDCLK to the SDRAMs; one
for each DIMM bank. All the control, data, and address sig-
nals driven by the memory controller are sampled by the
SDRAM at the rising edge of SDCLK. SDCLKOUT is a ref-
erence signal used to generate SDCLKIN. Read data is
sampled by the memory controller at the rising edge of
SDCLKIN.
SDCLK0
SDCLK[3:0]
SDCLK1
DIMM
0
SDCLKOUT
SDCLK2
SDCLK3
DIMM
1
Geode™ GX1
Processor
SDCLKIN
Delay
Figure 4-9. SDCLKIN Clocking
Revision 1.0
123
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